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TLC3578 / relationship between reference voltage and offset error

Other Parts Discussed in Thread: TLC3578

Dear support team,

Our customer is evaluating TLC3578 now.
I got some questions regarding TLC3578 from the customer.
So please advise me about it.

[Question]
The customer think that the relationship between the reference voltage (4.0 V) and offset error or gain error can be estimated from the equivalent circuit diagram in Figure 33 of the data sheet.
For example, when 0.4 V and -0.4 V are applied to the input of the ADC, if the reference voltage changes toward lower, he thinks that both the offset error will change in the negative direction.
And he thinks gain error will not change.
Is this thought correct?

In the result of his experiment, it seemed that the offset error is changing symmetrically about the zero point.
The offset error of 0.4 V changed in the minus direction and the offset error at -0.4 V changed
in the plus direction.
And it seemed gain error changed.
Is this behavior correct?

Best regards,
M. Tachibana

  • Dear support team,

    No one has replied to my question.
    I am being demanded from the customers now, so please let me know about my question.

    Best regards,
    M. Tachibana
  • .Hi M Tachinaba

    Sorry for the delayed reply

    TLC3578 has internal scaling circuit as shown in figure. 33.  

    For +/- 0.4V on input of ADC, mux input should see around 2.13V (for 0.4V ) and 1.97V (for -0.4V) with 4V reference. Now with reference moving towards lower value should change output code accordingly.

    Can you please let me know output code for +/- 0.4V input at ADC with ADC operating with 4V reference and lower reference value. What output code format are you using (BOB/BTC). Also can you send me calculations your customer did for gain and offset error for these conditions.

    Thanks & Regards

    Abhijeet 

  • Dear Abhijeet -san,

    Thanks for your reply.

    The customer is using BTC format.

    And result of his experiment is as follows,


    note: Value of "Output" is obtained by converting digital output into input voltage.

    Best regards,
    M. Tachibana

  • Hi M Tachibana

    If you reduce reference voltage then for same input voltage applied to ADC, code will change. This is due to gain error.

    For 4.1V to 4.06V of reference voltage change offset error will not change. Your observation is due to gain error.

    If you want to measure offset error, the best way is to define output code and apply input voltage to ADC to get that code. Difference between actual applied voltage and theoretical value of input voltage corresponding to that code would be your offset error.

    I hope this helps.

    Thanks & Regards

    Abhijeet

  • Dear Abhijeet -san,

    Sorry for my late reply.

    Regarding the signal scaling of TLC3578, I tried to calculate as attached.

    TLC3578_calculation.xlsx

    Is my understanding correct?
    When the REFP is 4 V, the negative full scale value does not become -10 V.
    Is the value corrected by calculation?

    Best regards,
    M. Tachibana

  • Hi M. Tachibana San

    I have gone through calculation sheet and calculations you did are correct. If you simulate same circuit in TI-TINA you can get same results.

    Negative full scale value may not match with -10V. This is due to the gain error of the device.

    One other suggestion is REFP pin of the device is designed to work from 3.96V to 4.04V. Please make sure you do not apply more than 4.04V at REFP pin of the device as this beyond recommended operating condition.

    Can you capture your results by keeping REFP within datasheet recommended conditions (3.96V to 4.04V) and see if results are consistent.  

    Thanks & Regards

    Abhijeet

  • Dear Abhijeet-san,

    Thanks for your great support.

    Today, I talked to the customer about this matter.
    And he understood almost.

    Thanks and best regards,
    M. Tachibana