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Queries on AMC7812B

Other Parts Discussed in Thread: AMC7812B, AMC7832


I have the following queries on AMC7812B

1) Do we need to connect additional buffer for DAC as well as ADC pins
2) What will be the effective output rate for each pin if i'm using all DACs .Consider i  take reading out of every ADC pin and processed and then made DAC to give output. Assume zero delay while processing.

Please suggest other parts which can have high performance but with similar or more number of DAC as well as ADC.

  • Howdy Bivin,

    1. The DAC output load current is specified in the datasheet of having a typical value of 10mA.  If the application requires larger current, then you may need to include a buffer or op-amp stage that is capable of driving this current value.  The ADC channels are internally muxed through one SAR ADC core, driving these ADC inputs with a low-impedance source is required to ensure that the internal sampling capacitor is driven to the correct voltage. The buffer also helps alleviate the affects created by neighboring charge injection.  The reason for channel interaction is the sharing of the internal sampling capacitor.  The internal multiplexer sequentially connects the active ADC channels to the internal sample capacitor.  When the multiplexer switches from one channel to the next, the new linked channel must be capable of driving the sample capacitor to the new voltage value by the conversion period.

    For more information on how to drive SAR ADC inputs please refer to the attached document from author Bonnie Baker:

    2.   The DAC output voltage settling time is listed as 3us (400h to C00h).  Communication speed should also be taken into account for a complete calculation of the DAC output rate -- a Single-Chip Write consists of 24 clock cycles.  Using this information the maximum DAC output rate is calculated as (3us + 24/SCLK freq).

    There are two modes for ADC conversion: auto and direct mode.  

    • Auto mode is a continuous operation. In auto mode, each analog channel within the specified group is convertedsequentially and repeatedly.
    • In direct mode, each analog channel within the specified group is converted a single time. After the last channel is converted, the ADC enters an idle state and waits for a new trigger.

    In auto mode:

    The ADC conversion rate can be calculated using the table in page 33.  I’ve looked at the register settings, and it seems to be set at a default conversion rate (throughput) of 500kSPS.  This sample rate is for a single channel in auto mode.  If more than one channel is selected, this conversion rate is divided by the number of channels selected in the ADC Channel 0/1 Register.  If 16 channels are used, the sample rate should be divided by 16 giving 31.25kSPS (32us).  

    In direct mode:

    The datasheet states that in direct mode, the conversion rate is limited by this throughput frequency (500kSPS), but the actual rate is determined by the rate of the conversion trigger – the conversion trigger is set via the /CONV pin or ICONV bit.  There is also a delay of up to 4 us to internally synchronize and initiate the start of the conversion process.  Using this information, I would calculate the maximum conversion rate to be (32us + 4us), 27.7kSPS.

    When synchronizing reads (for auto-mode), please be aware that a single ADC register read requires 2 24-bit frames.  Depending on the value of SCLK, you can calculate the transaction time as (48/SCLK freq). For a maximum SCLK frequency of 50MHz, this would result in a transaction time of 0.96us.  Additionally, the DAV pin should be used to synchronize reads if the part is set in auto mode.

    Please review the AMC7832/34/36, as these products also include large DAC/ADC channel count.

    Hope this information helps,

    Best Regards,


  • Hi Matt

    I would like to know whether TI have any similar IC with ADC and DAC pins with EXTERNAL reference with a CONTROLLER inside. As an example ADuC7122 but it don't have external reference.

    Regards & thanks

    Bivin George