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Looking for Xilinx Firmware from TIDA-00432 or other ADC12J4000 examples

Other Parts Discussed in Thread: ADC12J4000EVM, TIDA-00432, TSW14J10EVM, ADC12J4000

I am trying to read very high speed data (4 GSPS) from an ADC12J4000EVM.

This experiment is very similar to what I want to achieve:

Unfortunately I cannot find the Xilinx firmware in that project. Has anyone done a similar project?

Our setup is a VC707 EVM from Xilinx combined with a ADC12J4000EVM attached via FMC.

My main concern is how to get the data into the VC707 DDR-RAM quickly enough or how to read it out via Chipscope as a Stream or Dump.

Streaming via Ethernet would also be an option.

Also the document form TIDA-00432 references some VC709 firmware that was adjusted, I was wondering if anyone knows what code TI is refering to? My research has come up empty so far.

Also if anyone reads this, I would also be interested in sample code of how to stream UDP packets from a VC707 but this is a bit offtopic here.

Regards, Max

  • Max,

    Go to the TSW14J10EVM page and scroll down to the Software section.  There is a link for the Vivado project used for the KC7, VC7 and ZC7 families.  For further firmware support on the firmware you will need to contact/file a ticket with XIlinx.


  • Hello Ken,
    Can you get me in touch with the person at TI that did the TIDA-00432 project?
    The TSW14J10EVM only passes through data and only allows for a very limited capture of 65k Samples into the internal memory.
    I would also be very interested in what limitations lead to TI not using the DDR memory on the TSW14J10EVM firmware for storing samples. So getting me in touch with somebody familiar with TSW14J10 would also be very interesting to me.
    Regards, Max
  • Max,

    I have asked the engineer to respond to this thread.

    In general the projects that we create are typically done to prove a point.  In this case it was to show synchronization of 2 JESD204B links.  The intent of this TI Design was not to have the DDR controllers implemented to provide more memory.  For that you will have to implement the DDR controller and verify that it works as expected.  Using Block RAM was the easiest way to implement storage to prove out the synchronization concept without having to complicate it with implementation of the DDR controller.  It was a design choice made at the time of implementation.

    The TSW14J10 only passes the SERDES lines and provides a SPI interface into the FPGA to access the registers and the Block RAM in the FPGA.


  • Hi Max

    Ken's response is correct regarding this TI Design. The primary goal was to demonstrate the configuration and clocking method to ensure alignment between the multiple ADCs and the receiving FPGA.

    It is possible to add the needed DDR controller features to increase the storage capability or add logic to process the data in real time as would be needed in real applications. However those features were beyond the scope of this TI design.

    Best regards,

    Jim B

  • Hello Jim and Ken, I very much appreciate your replies and it is understandable that fully supporting another vendor's devices is not in TI's scope. In fact I am really happy you offer a product like the TSW14J10 to help people evaluate your High Speed ADCs on Xilinx hardware.

    The only thing that I am confused about is that I assumed that TIDA-00432 does not use the TSW14J10 code (which is the only VC707-firmware from TI I found online). The photo on the page shows that the ADC12J4000 modules are connected directly to the board and the documentation (tidu752) mentions using Chipscope to display data (vs. HSDC Pro used by TSW14J10)

    So Jim, if you were involved in the TIDA-00432 project, maybe you could answer me these two questions:

    1) In tidu752 it says "To download the software files, see the design files at TIDA-00432." It seems the firmware either got removed or was never uploaded, would you mind sharing it with me (under an NDA if needed). I am mostly interested the code to query ADC12J4000 over JESD.

    2) In tidu752 is says "The firmware for the VC707 platform is a modified version of the design firmware of the hardware demonstration provided by Xilinx for the VC709 platform." Does this refer to the file "" as shared in the Xilinx JESD204 lounge at

    Again, I am already very happy to get such a competent reply this quickly, it shows TI is doing a lot of things right (e.g. not shielding their experts from customer interaction). But I would be eternally grateful if you could share some code with me.

    Regards, Max