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HSMC-ADC-BRIDGE Rev C1 - LVDS P and M pins are switched around

Other Parts Discussed in Thread: HSMC-ADC-BRIDGE

I am trying to use a ADS41XX/58B18EVM board with an Altera MAX 10M50D Evaluation board, though a HSMC-ADC-BRIDGE Rev. C1 interface board.

The positive and negative LVDS pins seem to be switched around.

Seriously??? Am I missing something here?

Schematics with highlighted connections:

  • Hi,

    Could well be.  When the EVMs for the LVDS format devices were in layout, the instructions to the layout person would be to lay out the differential pair from the device to the connector as cleanly as possible, avoiding vias through the board to swap plus and minus sides to the connector.   If the positive/negative pairs get to the FPGA swapped, we would just take care of it in the FPGA firmware.  Inverting the data if needed is simple enough in the FPGA firmware.  Since the LVDS clock is usually Dual Data Rate, latching data on rising and falling edges, an inverted clock just means that the odd bits are latched on rising edge or the even bits are latched on rising edge, and vice versa.  Also easy to deal with in firmware.    Also, these EVMs were designed to connect to our TSW1200 FPGA card and later the newer TSW1400 capture card, and the adapter card just does a pass-through of the data from connector to connector to allow connection to the FPGA development board directly, but you still have to trace through the signal routing from the ADC to the FPGA to get the pin constraint file correct, and you may have to deal with signal inversion.


    Richard P.