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ADS7871: Frequent Occurrence of "PGA Valid 5" Bit Being Set under Single-Ended Input configuration.

Part Number: ADS7871

Hi,

I would like to seek some clarifications on the problem that i’m having with ADS7871. I noticed that for few chips that i’m working on, there are some weird issues that seems odd. First of all, i’ll like to point out that these issues do not normally occur with “good” chips but only happens with a few “bad” chips. These boards are machine soldered.

The ADS7871 is operating in single-ended input configuration. The gain is set to 1 and reference is set to internal (2.5V). I have verified that the reference voltage with a calibrated Fluke multimeter. The issue that i’m having is that when i try to sample 2.4V, i noticed that on the “bad” chips, i see frequent occurence of OVR bit set to 1 in Register 0. This error means something is wrong with the PGA side according to the datasheet. A check on the Register 2 reveals that PGA Valid 5 bit is triggered (Register 2 value = 0x20). This seems odd because i have verified that the configuration is indeed set to single-ended input. I have also measured the voltage on the ADC channel pin to make sure it is not hardware issue. It is just that the issue usually alternates between good reading (OVR bit is not set) and maybe bad reading (OVR bit is set) which makes it troublesome. Because it seems like at some time, the chips work okay but other times it just goes funky (PGA Valid 5 bit is set and it got nothing to do with the intended application which mainly deals with positive range).

Any idea as to why this is likely to occur and under what circumstances ? Take note that once i replace the “bad” chip with a new chip from the parts bin on the same board, the problem goes away.  

Much appreciated if anyone could shed some light on this problem. Thank you.

  • Hi Sharma,

    Thanks for the detailed description of the problem.

    Could you please share the following information so that we have some more clarity -

    1) Does the VLD5 bit get set irrespective of which channel you sample 2.4V on?
    2) Does the VLD5 bit get set only when you sample Vin > 2.4?
    3) Would it be possible to get an oscilloscope plot of channel input (>2.4V) with respect to device ground? Capture the waveform for atleast 2 sample periods.

    Thanks.

    Regards,
    Rahul
  • Hi Rahul,

    Thank you for the reply. Let me try to answer your questions:

    1) Yes.

    2) No because it happens below 2.4V (down to about 2.35V).

    3) Yes (Scope capture of LN6  = 2.414V [Measured with Fluke DMM])

    I would like add that the chip is operating at VDD = 3.3V. I apologize for not adding this in the first post.

    Regards,

    Sharma

  • Hi Sharma,

    Thanks for the additional details.

    Figure 10 in the data-sheet shows the transfer characteristics of the PGA. The PGA has upper and lower compliance limits beyond which its operation is non-linear. If the output of the PGA exceeds these compliance limits, the corresponding valid bit is set.

    At 5V VDD, the lower compliance limit is approximately 3.8V which is almost 75% of VDD. Hence at 3.3V VDD in your system the lower compliance limit is 2.475V which is very much marginal for the input you are sampling.

    To confirm if this is the root cause of the problem you are seeing, could you please increase device VDD to 3.6V and sample [2.5V > Vin > 2.35V]?

    Thanks.

    Regards,
    Rahul

  • Hi Rahul,

    Thank you for your help and sorry for the delayed reply. Yes, i have tested with higher VDD as suggested and got the chip to work as expected. However, since you have brought up Figure 10, we are now curious:

    1. How did you apply that to Single Ended configuration (what about the upper compliance?)?

    2. Is the compliance percentage relates to the references used by the comparators for fault checking ? Is there a typical value or min\max range to consider or the 75% based on the graph is a good rule of thumb?

    3. Any input as to why does the replacement chip solves the problem even at the same VDD ? Is the compliance level checked by the comparators may be affected by temperature (resistive divider?) ?

    Sorry for all these questions. We are a bit confused by the compliance limit and couldn't find much information on the fault detecting comparators. But, up to this point you have helped a lot and we are able to eliminate some doubts.

    Thank you.



    Regards,

    Sharma

  • Hi Sharma,

    1) As per Figure 10, at VDD = 5V, lower compliance threshold is 3.8V and upper compliance threshold is 4.5V. Hence, lower threshold will be asserted much before upper threshold. The compliance thresholds are applicable to the PGA irrespective of MUX operation.

    2) The compliance thresholds indicate a level of input/output swing beyond which the PGA is non-linear. Unfortunately, I could not find any additional data regarding compliance thresholds other than what is given in Figure 10. There is no min-max range to the compliance thresholds in the data-sheet. At room temperature VREF = 75% VDD will hold good.

    3) Replacement device would work because the compliance thresholds will have variation from device to device. Hence in some it may be 74% of VDD while others it may be 76% VDD. Going by your observation of 10 devices, it seems compliance threshold is >76% VDD for most devices. The remaining devices seemed to be at 75% VDD compliance threshold.
    VREF = 75% VDD will not hold good across temperature. This is because the comparator logic and its reference will drift with temperature. I would add 10% variation to the margin the thresholds have from VDD. Presently the thresholds have 25% margin from VDD at room temperature, an additional 2.5% will be expected over temperature. Hence, VREF < 72% VDD should hold good across temperature.

    I hope this helps.

    Regards,
    Rahul