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DAC39J82: DAC39J82

Part Number: DAC39J82

Can anyone please let me know for part number DAC39J82IAAV what are the source of power net for the -

LVDS output whether this is 1.8v or 0.9v standard (also what is its power supply net)

LVPECL inputs whether this is 1.8v or 0.9v standard (also what is its power supply net)

CML inputs whether this is 1.8v or 0.9v standard (also what is its power supply net)

it is not very clear from the datasheet

Q2. Does the DAC have power on reset feature, are IOUTA,B,C,D pulled to 0 on reset?

  • Request feedback from some one?
  • Siddharth,

    This is standard LVDS spec with 1.2V common mode. Programmable output current control LSB; allows output current to be scaled from ~2mA to ~4mA with 100 Ohm load on the receiver.

    For the CLK and SYSREF, there is no LVPECL standard. You can input max input 2Vpp differential, typical is 1.6 Vpp.  

     

    CML inputs whether this is 1.8v or 0.9v standard (also what is its power supply net)it is not very clear from the datasheet

    We are not sure what you are asking for. There is no CML standard. Please see the attachment for serdes input threshold info.

    Q2. Does the DAC have power on reset feature, are IOUTA,B,C,D pulled to 0 on reset?

    No. There is a rest input pin that you can toggle. The DAC outputs are held to midscale by holding TXENABLE input pin low at start up.

    Regards,

    Jim