DAC3151: DAC3151 - SYNC requirements

Hi,

I am not following you yet.  What kind of write are you referring to?  Writes to the SPI register space or writing data into the FIFO from the FPGA?

There only needs to be one initial SYNC event to initialize the FIFO pointers after a device is powered up.  But that needs to be a 'SYNC event' for both sides of the FIFO, and there are three ways to get that 'SYNC event'.   A pulse on the SYNC input for the write side of the FIFO with a pulse on the ALIGN input for the read side of the FIFO, or a pulse on the SYNC input for both sides of the FIFO with sync_only set, or a sif_sync event for both sides of the FIFO with sync_only set.

If the write and read sides of the FIFO get such an initialization event then that sets the FIFO pointers such that the read pointer lags the write pointer by a nominal 4 words, or about half of the FIFO.   From that point on, there never needs to be another SYNC event unless something disturbs the setup.  the pointers just go around and around based on their respective clock domains, DATACLK for the write side and DACCLK for the read side. 

if you do decide to have a periodic pulse on either SYNC or ALIGN, then period of that pulse should be divisible by 8 so that the 'event' simply resets the pointers to the position that they were to be in anyway and there is no disturbance to the FIFO.   Our TSW1400 I believe stores a pattern in memory that is written to the DAC in an endless repetitive loop, and that pattern must be of a length that is divisible by 8 and the FPGA issues a SYNC with every time the pattern repeats.  So with the TSW1400, a short pattern length means a more frequent SYNC and a long pattern length means a less frequent SYNC.  But after the first SYNC, there doesn't really ever need to be another one.   Unless the power to the DAC is disturbed or there is some other 'disturbance' to the configuration of the DAC. 

Regards,

Richard P.