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ADC1175-50: ADC1175-50CIMTX/NOPB with 3.3V digital interface

ttd
Mastermind 7670 points
Part Number: ADC1175-50
Other Parts Discussed in Thread: ADC1175, SN74LVC8T245, ADC1173

 

Dear Technical Support Team,

 

I have a question about ADC1175-50CIMTX/NOPB.

 

I'd like to use 3.3V digital interface with FPGA.

Datasheet page.17 shows below.

 

1.)

Can I use 3.3V digital Interface with DVDD 11pin supplied 3.3V?

For example,

 

DVDD 11pin: 3.3V

DVDD 13pin: 5V

 

2.)

If it is possible to use 3.3V interface, do you provide VOH/VOL/VIH/VIL specification with 3.3V?

Datasheet shows only 5V supply.

 

3.)

Pin 11 should never exceed the pin 13 potential by more than 0.5V.

Is it correct for power sequence below?

 

Power on： 5V(13pin) ⇒　3.3V(11pin)

Power off: 3.3V(11pin) ⇒　5V(13pin)

 

4.)

Datasheet page.2 "BLOCK DIAGRAM" shows DVDD 11pin supply for ADC output drivers.

But following description said "pin 13 is used only to provide power to the ADC output drivers"

Which is correct?

 

-----------------------------------

Pins 11 and 13 are both labeled DVDD. Pin 11 is the supply point for the digital core of the ADC, where pin 13 is

used only to provide power to the ADC output drivers. As such, pin 11 may be connected to a voltage source

that is less than the +5V used for AVDD and DVDD to ease interfacing to low voltage devices. Pin 11 should never

exceed the pin 13 potential by more than 0.5V.

-----------------------------------

 

Best Regards,

ttd

  • 0
    TI__Mastermind 43930 points

    Hi ttd

    The ADC1175-50 datasheet pin description table states that pin11 and pin13 are both DVDD pins and should be at the same voltage. .

    The slower ADC1175 (20 MSPS max sample rate) does allow a lower voltage on pin 11 and I believe some of that wording was mistakenly left in the ADC1175-50 datasheet when the higher speed device was developed. To achieve the needed device performance at 50 MHz clock rate the output drivers for the -50 device must be supplied at the same +5V level as the other digital sections.

    If you need to interface the ADC output data bus to a 3.3V FPGA bank, I recommend using a level shifting device like the SN74LVC8T245 to perform the voltage translation from 5V to 3.3V logic levels. Doing this will also help to minimize the capacitive loading on the ADC CMOS data output drivers.

    I hope this is helpful.

    Best regards,

    Jim B

  • 0 in reply to Jim Brinkhurst1
    Mastermind 7670 points
    Hi Jim B,

    Thank you for your reply.

    ADC1175 datasheet shows same description of ADC1175-50,
    but the range of supply voltage (AVDD, DVDD) is +4.75V to +5.25V on OPERATING RATINGS.
    Is it really ok to use 3.3V DVDD(11pin)?

    I guess ADC1173 is ok to use DVDD 3.3V, because the range of supply voltage (AVDD, DVDD) is +2.7V to +3.6V.
    It's 15MSPS AD converter and same description below.

    ADC1173 Page.20
    ------
    Pins 11 and 13 are both labeled DVDD. Pin 11 is the supply point for the digital core of the ADC, where pin 13 is
    used only to provide power to the ADC output drivers. As such, pin 11 may be connected to a voltage source
    that is less than the +5V used for AVDD and DVDD to ease interfacing to low voltage devices. Pin 11 should never
    exceed the pin 13 potential by more than 0.5V. Note that tOD will increase for lower pin 11 voltages.

    Best Regards,
    ttd
  • 0 in reply to ttd
    Mastermind 7670 points
    Hi Jim B,

    Is it possible to connect CLK and PD of ADC1175-50 with FPGA 3.3V interface directrly(no level shifter)?
    VIH is 2.0V, so it looks possible.

    Best Regards,
  • 0 in reply to ttd
    TI__Mastermind 43930 points

    Hi ttd

    Those 2 inputs can accept a signal from a 3.3V FPGA bank as long as the minimum output voltage from the bank is >=2.0V.

    For the CLK, the performance of the ADC will be impacted if the RMS jitter is greater than around 25ps. If the CLK signal from the FPGA could have more jitter than this I would recommend adding a dedicated clock oscillator. If you are unsure whether this is needed you can include this as an assembly option.

    Best regards,

    Jim B