I wonder how the ADC121Sxxx behave when nCS is asserted low and more than 16 clocks are supplied.
Regards
Arne
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I wonder how the ADC121Sxxx behave when nCS is asserted low and more than 16 clocks are supplied.
Regards
Arne
Hello Arne,
Please see section 9.4.1 in the datasheet.
"Sixteen SCLK cycles are required to read all of a conversion word from the device. After sixteen SCLK cycles have elapsed, CS may be idled either high or low until the next conversion. If CS is idled low, it must be brought high again before the start of the next conversion, which begins when CS is again brought low.
After sixteen SCLK cycles, SDATA returns to TRI-STATE. Another conversion may be started, after tQUIET has elapsed, by bringing CS low again."
The extra clock pulses will not start another conversion, they will be ignored. CS must be brought high and then low again to start the next conversion.
Mike