ADC32RF45: SBAA226 configuration file

Hi,

I have asked the datasheet authors what files are being referred to.  I will let you know what I find out.  My early speculation from looking at the document and at the path name for that lit number is that the literature number points to a zip folder of files, while the path name seems to indicate a folder of pdf files.   I suspect the path name might really need to point to a different folder.  but we will find out.

Regards,

Richard P.

Hi Richard

I reviewed this configuration files <SBAA226.zip> attached in this post  I can not find registers described in IL_Config_Nyqx_chA/B.  Currently we are not initialized these registers.  It seems to me lot of registers setting on other pages are not in data sheet.  Please help.

Thanks

Sam

Sorry I meant Non Linearity Trims for Nyquist both Channel A and B.

Thanks

Sam

Hi,

there are a *lot* of special registers in the ADC32RF45 that should be set for purposes of optimizing performance and these registers are not documented as to the internal function of each and every one.   Usually as a device is nearing the end of its development there will be a lot of trim settings that become finalized - things like maybe 10 microamps of bias current for an internal circuit compared to maybe 15 or 5 microamps.   That kind of thing.  And usually these trim values get hard coded into fuses or hardcoded in the design of the silicon.  But this device has a *lot* of such trim, and some *are* set in design, some are set by fuses in manufacture, but some were left open and should be set after every power cycle by SPI writes.   The authors of the datasheet have been working on how to make these special registers clearly documented.  One early draft of the datasheet had a big table of address/data pairs with the instructions to essentially 'just write these values'.  The current datasheet they put that info in the zip file with the link to download.   But things that you see in those files that set mode of operation and have datasheet descriptions you may change to become what you wish to see for the mode of operation, but those *other* things that are in those files you should just keep as is and do them.    And so far I am referring to those files you see there that are not the non linearity trims.     For those files that are the non linearity trims - almost all of those registers in those files are trim values that are to registers that are not in the basic register map.   These also should simply be done as you see them in the files.   You may have seen from the datasheet that each channel of the ADC is really a 4-way interleaved composite of four sub_ADCs.  There is digital logic following the four sub_ADCs that performs offset correction across the four sub_ADCs.   There is also after that a block of logic to adjust for non-linearities in the device, and this nonlinearity correction is highly frequency dependent.  So there is a file of trim values for the NL correction that is meant for when your input signal is in the 1st Nyquist zone, another file for when you are in the 2nd Nyquist zone, and another for 3rd Nyquist zone.  You should just perform these SPI writes to the ADC after all the other configuration has been done.   Without the NL config file loaded, there may be worse performance observed  on the 2nd and 3rd harmonics and some of the intermodulation products than otherwise would be seen if the file were loaded.

Regards,

Richard P.

Hi Richard

from the zip file the NL_Config_Nyqx_chA as follow

0x4003 0x00 //chA Non Linearity Trims for Nyq2. Remember the sequence of programming the config files is Powerup_Analog_Config-->IL_Config_Nyqx_chA-->IL_Config_Nyqx_chB-->NL_Config_Nyqx_chA-->NL_Config_Nyqx_chB-->JESD_Config

0x4004 0x20 //...

0x4002 0xF8 //...

From data sheet, the page for NL_Config_Nyqx_chA should be 0x680000. Is it mistaking on the setting or I missed something?

Thanks

Sam

hi,

if you look inside the files for IL config, you would see early on that setting the Nyquist zone and enable bits *are* in that page.  The registers you are looking at in the NL config files are many, many special trim registers that are not individually documented in the datasheet.  They just are what they are.

0x4002 0x00
0x4003 0x00  //Main digital page selected for chA
0x4004 0x68
0x6044 0x01 //Program global settings for Interleaving Corrector
0x6068 0x04 //...
0x60FF 0xC0 //...
0x60A2 0x09 //Progam nyquist zone 2 for chA, nyquist zone = 1 : 0x08, nyquist zone = 2 : 0x09, nyquist zone = 3 : 0x0A
0x60A9 0x03 //...

Regards,

Richard P.

Hi Richard

The reason I asked because we had 4 boards with product ADC parts, 3 of the boards working much better than the fourth one.  I put scope probe on one of JESD link, three of the boards working send K28.5 after the first ADC initialization, occasionally it took 2 or 3 attempts to get ADC send out  K28.5.  The fourth board getting worst, 50% I can not K28.5 after many attempt reinitialize the ADC. the only thing get out of this by power cycle the board and hope the card come back.  Do you have any suggestion for debugging this issue?

Thanks
Sam

Hi,

it depends on just what you are seeing.   When SYNC is asserted, the ADC will be sending out K28.5.   So it depends on whether you are not seeing the K28.5 leave the ADC during SYNC when probing the serial data lines or if the SERDES in the FPGA is failing to detect the pattern reliably.   Check the logic levels of the SYNC signal and the common mode of the signal at the SYNC input pins of the ADC, assuming you are using the LVDS SYNC.  You should have adequate swing - usually about 700mV peak to peak diff for an LVDS driver - and that the common mode of the signal is around 1.2V.   If the ADC is not able to reliably see the SYNC signal then that could be a problem.   If the ADC is able to see the SYNC signal and the ADC is outputting K28.5, then for the faster lane rates it may be that the FPGA is getting too many bit errors to complete link initialization.   What is your lane rate, or what is your sample rate and mode of operation?  At lane rates of around 12Gbps we had to enable the adaptive equalization feature in the FPGA as well as set the lane de-emphasis in the ADC to about -6.2dB to get an error-free link operation.  Your FPGA and lane rate may be different.

Regards,

Richard P.

Hi Richard

Thanks for your response, on two silicon failed.  ADC failed to send K28.5 out when the sync asserted.  This observation by looking at scope one of the JESD lane to the FPGA.  Regarding Sync signal, yes it is LVDS and it generates directly from Xilinx FPGA as LVDS signal, it meets LVDS requirements. 

Thanks

Sam