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ADC12J4000: Getting 8 Gsps by using two interleaved 4Gsps ADC12j4000 s

Chandra Kanth Pamarthi
Prodigy 15 points
Part Number: ADC12J4000

Hi,

We want 6 Gsps ADC for our application, and the there is no specific ADC module which meets this requirement also. So, we want to use two interleaved 4 Gsps ADCs (ADC12J4000). We will 180 degrees phase shifted clocks for theese two interleaved ADCs. Can this design gives good results (interms of SFDR, Enob)?

In the data sheet is mentioned that the core uses an interleaved calibrated folding and interpolating architecture. Could you please let us the know the number of interleaved ADCs that are present in the single ADC12j4000 4Gsps ADC??

 

 

Thanks in advance.

Regards,

Chandra Kanth

  • 0
    TI__Expert 3835 points

    Chandra,

    There are 4 internal ADC cores that are interleaved, sampling at 1 GSPS.

    When interleaving ADCs, there are a lot of issues such as ADC Gain and DC offset. Calibrating the device and help to minimize the gain and offset. Timing is often the other issue here. Even if the clocks applied to the 2 ADCs are exactly 180 degrees out of phase, part to part variations in aperture delay will result in non-ideal interleave timing for the actual sample events. Practically this means a very fine step size adjustable time delay is required for both ADC clock paths. The ADC itself does not include any sample timing adjustments.

    The timing adjust circuit needs to have fine enough steps to allow the timing mismatch to be adjusted to a very small value (sub ps ideally), and enough adjustment range to cover part to part variations between devices. Assuming Voltage and Temperature are similar, the main contributing factor is process variation. Design simulation estimates give a variation of aperture delay due to process variation on the order of +/-20%. For a typical aperture delay of 0.64ns, the variation could be +/- 128ps for each device.

    Achieving this delay adjustment range and step size on a clock at 4 GHz with significantly adding jitter is the primary challenge of implementing the interleaved ADC solution with this device.

    The amount of spurs due to offset, gain and timing mismatch can be calculated, based on the amplitude and frequency of the input signal, and the amount of mismatch. Spurs at Fs/2 due to offset and Fs/2-Fin due to timing and gain mismatch are the main degradations.

    Have a look at the following documents that describes various spurs in general and detailed calculation methods:

    http://www.ti.com/lit/an/slaa617/slaa617.pdf

    http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=915383