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ADC12D1800: adc12D1800 clock spur at 1/4 clock frequency

ajayt
Genius 9555 points
Part Number: ADC12D1800


Hi Team,

We have built 5 PCB's using the TI ADC12D1800CIUT/NOPB and they are all producing a similar result with a noise spike at 825MHz, 1/4 of the sampling clock rate 3,300 MHz.

A Calibration cycle with no input signal has no effect.

We are at a loss to know what to do to try to reduce the spike.
 

Can you offer some suggestions?

  • 0
    TI__Mastermind 44680 points

    Hi ajayt

    The ADC12D1800 device uses an interleaved architecture to achieve the high sampling rate. In 2-input mode, with a sample rate of 1800 Msps each input is sampled by 2 internal converters each running at Fs/2 or 900 Msps.

    In 1-input mode (DES or Dual Edge Sampling mode) the single input is sampled by all 4 internal converters. For a sample rate of 3.6 Gsps each interleaved converter is running at Fs/4 or 900 Msps.

    The spur at Fs/4 in 1-input mode is caused by minor offset mismatch between the 4 interleaved converters. Proper calibration will minimize this spur, but there is no way to eliminate it completely.

    For more details on this device architecture, the different spur sources and mitigation techniques please take a look at this document, in particular Section 2.1 Interleaving Spurs.

    http://www.ti.com/analog/docs/litabsmultiplefilelist.tsp?literatureNumber=slaa617&docCategoryId=1&familyId=82

    I hope this is helpful.

    Best regards,

    Jim B