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DAC5687EVM: dac5687 input clock

Part Number: DAC5687EVM

Hi everybody,

I have a DAC5687EVM board and want to convert 16 bits digital data to analog signal. I got the digital data from a xilinx FPGA board. The DAC5687EVM board requires a 0-1Vpp square wave clock signal. The FPGA board provides a 0-3.3Vpp square wave up to 100 MHz. The questions are:

1) How can I attenuate the clock signal obtained from the FPGA?

2) Is there any other solution for DAC5687 EVM clocking?

3) How can I get 0-1Vpp low jitter high frequency square wave?

Thanks a lot...

  • Yunus,

    Normally an FPGA clock output has poor jitter performance and is usually not recommended to be used as a sample clock for data converters. I would suggest you look into using a TI CDCE62005 clock generator. See the attached schematic for an example using this part with a TI DAC.

    Regards,

    Jim

    DAC328XEVM-SCH_revE.pdf