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DAC6578: About I2C bus

Dice-K
Mastermind 6730 points
Part Number: DAC6578

Hello,
I have two questions about DAC6578.

With a product using DAC6578SPW, I do CPU and I2C bus connection.
I connect other slave devices (example EEPROM) to the same bus, too.

With other devices, the following methods are recommended as measures for the bus access abnormality (don't open SDA) by the access interruption.

Input "dummy-clock *14" and "START-condition *2"

So, I have questions.

(1)
Do these measures not become a problem for DAC6578SPW?

(2)
As a coping method when bus access abnormality occurred in DAC6578SPW, are these measures effective?
Please teach me the recommended method if it is not effective.

Regards,
Dice-K

  • 0
    TI__Guru 53283 points

    Dice-K,

    Without knowing what device you are using as the I2C master it is difficult to know if your syntax is correct, could you please share that information?  It would also be beneficial if you could post oscilloscope images of the communication.  More over the datasheet contains a section describing the I2C communication format on page 28.

    Paul

  • 0 in reply to Paul_Frost
    Mastermind 6730 points
    Hello Paul,
    Thank you for your reply.

    I change the way of questions.

    This measure is for other IC.
    Input "dummy-clock *14" and "START-condition *2".

    Therefore, please answer that it is no problem for DAC6578 if this measure gives DAC6578 no influence.

    Best regards,
    Dice-K
  • 0 in reply to Dice-K
    TI__Guru 53283 points
    Dice,

    There will not be an issue with the two devices sharing a same I2C bus if they have different addresses. Table 3 in the DAC6578 datasheet lists all the addresses that the DAC6578 is capable of using. You must verify that the other devices on the bus (EEPROM for example) has a different address than the DAC.

    Paul
  • 0 in reply to Paul_Frost
    Mastermind 6730 points

    Hello Paul,
    Thank you for your reply.

    About Q2.

    Is there a coping method when bus access abnormality occurred in DAC6578SPW?
    If there is not a method, please answer me so.

    P.S. of Q1
    Because DAC6578SPW is TSSOP, I see Table-4.

    Best regards,
    Dice-K

  • 0 in reply to Dice-K
    TI__Guru 53283 points

    I suppose I am confused on what you mean when you say there is 'abnormal' bus access.  The DAC6578 will not take any action from any I2C activity if the first byte does not have the correct address.  

  • 0 in reply to Paul_Frost
    Mastermind 6730 points

    Hello Paul,
    Thank you for your reply.

    'Abnormal bus access' means 'the bus access abnormality (don't release SDA) by the access interruption'.

    Other IC has a countermeasure as below.

    Input "dummy-clock 14-times".
    Input "START-condition 2-times".

    Does DAC6578 have a countermeasure as above?

    If there is not a countermeasure, please answer me so.

    Best regards,
    Dice-K

  • 0 in reply to Dice-K
    Mastermind 6730 points
    Hello Paul,

    I got additional information from my customer.

    "Dummy-clock *14 and START-condition *2" is one of the return way of the following case.
    A CPU is reset during I2C access.
    An I2C bus state of the slave device becomes abnormal. (A slave device continues driving SDA to Low.)

    Please give me an answer in consideration of the above.

    Best regards,
    Dice-K
  • 0 in reply to Dice-K
    Mastermind 6730 points
    Hello Paul.

    "Dummy-clock *14 and START-condition *2" is the way of 'Software Reset' of EEPROM.
    rohmfs.rohm.com/.../br24t128-w-e.pdf
    Please refer to page-16.

    DAC6578 has 'SOFTWARE RESET FUNCTION'.
    It is described in the page-39 of SBAS496A.

    Best regards,
    Dice-K