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DAC8801: DAC Output when Clock is disabled, but SDI and CS is active

Part Number: DAC8801

What will the DAC output do if the Clock input is not transitioning, but SDI and CS are moving as if the clock is moving.

We have a circuit that when the system detects a system condition, it disables the clock by setting it low.  The CS and SDI continues to function as if it has a data to store to the DAC.  We are finding that the DAC does not always hold it's last value just before we disable the clock.  Is it possible that a new D13 value is being stored into the DAC when the CS transitions low to high?



  • John,

    These older datasheets aren't as verbose as what we strive for these days. Please give me some time to check with the design team in the design database to answer this.
  • John,

    I sat with the Design Engineer and looked at the digital design together. The SDI pin feeds directly into the digital block that contains the DAC data register. The CLK pin is connected to an AND gate whose other input is connected to the inverted CS input. So if CS is toggled low the AND gate is sort of enabled and if CLK is toggled data would begin to be latched by the digital block, but without clocks no matter what you do on SDI the DAC data will not change.

    One possibility that comes to mind is what if (not sure if it's possible or not) this "system condition" occurs in the middle of toggling CLK during an SPI frame. Some SPI digital blocks implement counters that would only allow the data register to be updated if the appropriate (or greater) number of clocks are issued but parts at the time of release for DAC8801, including DAC8801, did not include such counters. So even if it's an "incomplete frame" the SDO data will still be shifted into the data regsiter and is perhaps what is causing this behavior. Maybe this is worth validating in your system to help further the debugging effort.

    The only other possibility would be "clock-like" transients AC coupling into the CLK pin during this time.

    My recommendation, not sure if it's applicable or not, would be to hold the CS pin as opposed to the CLK pin.

    Let me know what you think and we can proceed.
  • itKevin,

    Thank you so much for your fast response.  I believe you have answered our question. 

    We also thought about the mid frame interrupt.  Our test people have indicated that they are in control of the sequence and wait long enough before issuing the disable.  They are verifying it again though.

    Of course as a card designer there is always a chance of noise.  I believe we have enough low impedance that the chance should be low.  But if it continues we will have to put a probe on there and verify.  Thank you for your thoughts / suggestions and comments.  The CS disable is a good suggestion, but we used clock since that goes to multiple DAC's and CS's go in individual DAC's (currently we are controlling 16 DAC's).  In our design SDI is shared, Clock is split into two signals and then shared, CS is the only individual signal.

    Have a great day!

    -John Gray

  • John,

    Happy to help.

    Please let me know the outcome of your probe investigation and if we need to provide further assistance. As I mentioned in my earlier post, though, the digital design appears to be pretty straightforward such that I was not able to observe how this unexpected behavior would be possible on account of the DAC alone.

    Of course that is not to say it is impossible :) If your study suggests it is the DAC we can dig deeper with bench tests and/or simulation.