Other Parts Discussed in Thread: ADC121C021
I need to read this ADC121S021 with the GPIO pins of a microcontroller that runs at 4 MHz.
The input of the ADC is connected to a 100 kOhm/220nF filter. The application takes a single sample, then quickly turns off the ADC, waiting for longer time (several seconds..hours) to repeat.
I've implemented a bit-banged SPI readout function. It turns on the ADC power, after a while it activates CS_N and then clocks the data out as fast as possible. The first sample is ignored, the 2nd sample is used.
The data of this 2nd sample corresponds nicely to the input voltage; it seems to work OK with RMS noise below 1 LSB.
However, when looking at SCLK, CS_N and SDATA at the logic analyzer, I see that I violate the timing requirements from the PDS:
- The high time of the SCLK pulse is 250 ns wide,
- The fastest low time of SCLK is 1 us (due to read and store operations after each falling edge)
So this is more asymmetric than allowed (Thigh < 0.4 Tsclk, Tlow > 0.4 Tsclk).
The controller PCB cannot be changed so there is no option to generate a proper clock with a dedicated SPI peripheral or higher clock frequencies.
I could change the SCLK shape to be symmetrical by making the high pulse 1 us long, just like the low pulse.
But then the sample rate drops to 25 kSps (at least, based on f=1/(20xTsclk)), where all specs hold for speeds from 50 kSps.
Since this is to become part of a reliable product, I'ld like to know:
- what can go wrong when I keep this deviation from the timing requirements? Which ADC specs can be affected?
- what is better: too asymmetric and fast, or symmetric and a bit too slow?
I am aware that there are no guarantees outside the datasheet limits, but any hints or reasoning based on the ADC's inner guts would be greatly appreciated.
Suggestions for better suitable parts are also welcome.