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ADC121S021: readout with GPIO on slow microcontroller?

Part Number: ADC121S021
Other Parts Discussed in Thread: ADC121C021

I need to read this ADC121S021 with the GPIO pins of a microcontroller that runs at 4 MHz. 

The input of the ADC is connected to a 100 kOhm/220nF filter. The application takes a single sample, then quickly turns off the ADC, waiting for longer time (several seconds..hours) to repeat.

I've implemented a bit-banged SPI readout function. It turns on the ADC power, after a while it activates CS_N and then clocks the data out as fast as possible. The first sample is ignored, the 2nd sample is used.

The data of this 2nd sample corresponds nicely to the input voltage; it seems to work OK with RMS noise below 1 LSB.

However, when looking at SCLK, CS_N and SDATA at the logic analyzer, I see that I violate the timing requirements from the PDS:

- The high time of the SCLK pulse is 250 ns wide,

- The fastest low time of SCLK is 1 us (due to read and store operations after each falling edge)

So this is more asymmetric than allowed (Thigh < 0.4 Tsclk, Tlow > 0.4 Tsclk).

The controller PCB cannot be changed so there is no option to generate a proper clock with a dedicated SPI peripheral or higher clock frequencies.

I could change the SCLK shape to be symmetrical by making the high pulse 1 us long, just like the low pulse. 
But then the sample rate drops to 25 kSps (at least, based on f=1/(20xTsclk)), where all specs hold for speeds from 50 kSps.

Since this is to become part of a reliable product, I'ld like to know:

- what can go wrong when I keep this deviation from the timing requirements? Which ADC specs can be affected?

- what is better: too asymmetric and fast, or symmetric and a bit too slow?

I am aware that there are no guarantees outside the datasheet limits, but any hints or reasoning based on the ADC's inner guts would be greatly appreciated.

Suggestions for better suitable parts are also welcome.

  • Hi Marco,

    With the setup you are using there is no way that you can get the part working within specifications by increasing the time of tch.

    tch tcl tclk fclk tcl,h,min sps
    0.00000025 0.000001 0.00000125 800000 0.0000005 40000
    0.0000005 0.000001 0.0000015 666667 0.0000006 33333
    0.00000075 0.000001 0.00000175 571428 0.0000007 28571
    0.000001 0.000001 0.000002 500000 0.0000008 25000

    I am not sure if there are any problems associated with having the clock so asymmetrical. I think it I were using the part like this I would try having tch at either 750ns or 1us so that it is more symmetrical.

    One of the problems that can happen when running at a slower sampling rate than specified is having the internal sampling capacitor sag during the measurement. I don't think this will be a problem at 25ksps. As you mentioned there are no guarantees when operating out of the specifications, but I think this would be the best set up with the system you have to work with.

    Another option is to try the ADC121C021. This device uses I2C communication, so it is inherently much slower. It can run with a 100kHz or 400kHz clock.

    Mike
  • Mike, thanks for the clear answer. A first quick test with 750ns/1000ns goes OK, so I think I'll stick with that as long as possible.
    On second thought I might be able to get the low clocktime to 750 or even 500 ns by inlining some assembly code. And the ADC121C021 is a superior option that I should have spotted earlier ;-) but now requires most work of the three options.