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ADC08060: data valid position related to clock edge

Part Number: ADC08060
Other Parts Discussed in Thread: ADS831, ADC1175,


It is mentioned in adc08060 (adc1175, ads831, etc) datasheet that the output data is valid just after the rising edge of the clock, does it mean to read the data with rising edge of the clock?(or otherwise, to read data in high level of clock?)

What is the status of output data at the falling edge of clock? is the previous data valid in falling edge?



  • Aseok,

    We are looking into this.



  • Hi Aseok

    The ADC08060 output data updates tOD after the rising edge of CLK. The datasheet specification for tOD is 8.2ns typical and 12 ns maximum. The typical tOH value is 4.2 ns, but no minimum or maximum is specified.

    If CLK is at the maximum frequency of 60 MHz, it will have a period of 16.67ns. So with the typical tOD, the new data will be available 8.2ns later, or near the falling edge of CLK if the CLK duty cycle is 50%.

    Given this timing relationship it would be appropriate to latch the data into the receiving logic device using the rising edge of CLK. If CLK is significantly slower than 60 MHz then it would be possible to use the negative edge of CLK to capture data instead.

    If possible the logic device should have some adjustment of the capture edge using an internal clock delay/control element. This can be used to fine-tune the capture event if necessary.

    Best regards,

    Jim B