DAC3164: Datasheet deficiencies...

Radar,

Has this question been answered?

Regards,

Jim

No, I still have the same questions posted above.

Hi,

My apologies.  I spent quite a bit of time composing a response back when your posting first arrived but the response seems to have not made it to the forum and just vanished.

Yes, there have been some deficiencies in the datasheets for that family of devices and these deficiencies are in the process of being corrected.   There are three datasheets covering a family of six devices covering single and dual channel devices, with 10bit and 12bit and 14bit versions of each.  Some of these datasheets have already been edited recently to address some of the concerns and all of the datasheets are currently in edit to hopefully wrap it all up.  Editing datasheets are a bit more involved than other documents as I have to go through a controlled process for edit and review.  The DAC3164 datasheet is one of those that hasn't yet had a revision since it was released and there are numerous typos and omissions to be fixed.

In general, if you see the information you are looking for in one of the other two datasheets for that family then you can use that information, such as looking into the DAC3174 datasheet for the LVPECL specifications that were added recently.  The LVPECL input specifications were one of the things that were completely missing from the original datasheet, and what is holding up the release of the revisions to the datasheets is that characterization data is being taken now to include the setup/hold timing for the ALIGN input relative to the DACCLK input.  (also, the LVPECL inputs share a common design and CMOS process with the DAC3282 device, so information on the LVPECL input structure and specs from that datasheet such as figure 35 are valid also for this device - but that information would not be readily apparent without knowing the design history of the two devices of course.)

For digital latency, I *do* see a spec in all three datasheets for digital latency, but there were typos in two of the datasheets for the units that attach to the specified number.   The overall latency is usually a typical number of clock cycles due to the digital logic plus a fixed amount of delay due to the input/output buffers. The typical latency for all of the devices in the family are 26 cycles of DACCLK, plus the tpd propagation delay of input clock to output buffer,  The digital latency is specified as a typical because there will be some uncertainty of a few clock cycles of the latency through the FIFO depending on the phase of DATACLK to DACCLK and the way the FIFO pointers are initialized with SYNC and ALIGN or sif_sync. If the latency through the 8-word FIFO is a nominal 4 words, then the overall digital latency would be 26 DACCLK cycles, but the FIFO latency could be one or two or three cycles more or less than that depending on conditions.

Regards,

Richard P.