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DAC39J82EVM: Please send LMK04828 Hexfile

Part Number: DAC39J82EVM
Other Parts Discussed in Thread: LMK04828,

Could you provide the hex file for the LMK04828 used for this eval board: DAC39J82EVM?


  • Kurt,

    Are you asking for the register information? This will depend on the setup of your system. If you are using a DAC39J82EVM with the DAC GUI, after you load the setup parameters on the quick start tab, double click in the lower left of the GUI and a log file will open. This will show you every register value that is being loaded both in the LMK and DAC device. Follow the instructions in the attached file for saving this data.



    DAC Log file.pptx

  • Yes, that's what I'm asking. Where can I find the default load for the LMK04828 for the EVM?
  • LMK_settings_737p29_Fs.csvKurt,

    If we are using a LMFS = 4211, with a input data rate and output rate of 737.28MHz, the serdes rate will be 7.3728Gbps. The default settings for the LMK in this mode are in the attached file.




  • I was also wanting any config file you have for the DAC registers.  Could you send that too please?

  • I will likely have a few more questions.  And, is there some tool to auto-calculate the values for me? I tried the eval tool, but that doesn't seem to do any calculations.

    Register:                   Question

    -----------                     --------------

    0x1E                          Can you explain how sync works from the SIF vs "sync_out from JESD?"  Is there anything that explains this register more clearly in some detail?

    0x1F                           The documented default does not match what's in table 61. As with above, when do I set 0x1F to 0x9982 to initiate a sif_sync, and what does this do, actually?

    0x31                          In a few places, the note under the default value says "FUSE controlled."  What does that mean?


  • Jim,

      At your advice we removed the large array of resistors and the LFCN-900+ and replaced with a direct connection to a DLFCV-1000+.  Do you see any problems with that? I'm inserting a picture of the change.

    Do you see a problem with this change, noting that there's a 100 Ohm resistor between MOD_I_P and MOD_I_N?

  • Kurt,

    Sorry for the delay.  Jim is out on vacation this week.  I will try to cover as best I can.

    Your previous circuit seems to have some DC shift network with a bypass cap for high frequencies.  This implies that you have different DC bias/common mode requirements for the DAC vs the IQ modulator.

    My only question is if this requirement is still needed with the 2nd circuit.  Are you still meeting the common mode requirements of the IQ mod?

    Also the DAC requires a resistive termination at the IOUT pin (current source).  Do you need a 25 or 50 ohm to gnd on IOUTP and IOUTN?  I'm not very familiar with the minicircuits LPF and how it needs to be connected.  The data sheet seems to imply the only components in the filter are LC and you may need a source and termination resistor before and after the filter.


  • That's what I was expecting to hear.  I think I do need a 50 Ohm to ground on IOUTP/N.  Additionally, I think we're ok in terms of common mode.


  • Ok - keep in mind the DAC will source an avg of 15mA DC (mid level) when there is an AC signal so depending on the load of 25 or 50 ohms you will have this as the common mode - as long as the IQ mod is ok with this and the swing on IOUTP and OUTN then you should be ok.