This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADS62P29: Crosstalk from clock to signal

Part Number: ADS62P29

Hello,

I have got some problems with my ADS62P29EVM and I  was wondering if anyone could offer some thoughts. The schematics of ADS62P29 is at 

I used the default clock configuration, clock comes from J19. The clock is a 1.5Vpp, 100MHz square wave in burst mode.

The differential analog signals for both channels are some pulses, also in burst mode (relatively low duty cycle). The signals come with a 1.5V common mode voltage so I removed the transformers (T1, T2, T3 and T4) and replaced each transformer with two 0ohm resistors. I did this because the input signal will be distorted when the transformers remove the DC component.

Now when I use a probe to check the analog signal, on the oscilloscope I can see there are additional small spikes to the signal and the spikes are synchronized with the clock. If I disconnect the clock from the evaluation board, the spikes will disappear.

If I remove the 0ohm resistor on SJP7 (in this case, the clock will not reach T6, neither the ADC ), the small spikes will also disappear. So from this observation I conclude that there is crosstalk from the clock to the signal. However I don't know how the crosstalk occurred. Could there be anything wrong with the transformer (T6) or the ADC? 

Any thoughts would be helpful. Thanks.

Lingmei

  • Lingmei,

    Without the transformers, how are you creating a differential analog input? Did you remove R67 and R65 as well? Why do have to burst the clock? This could be the main problem as this creates more energy than a continuous clock. Can you try a continuous clock and see if the noise is still present? If you have to burst the clock, did you try lowering the amplitude?

    Regards,

    Jim

  • Hi Jim,

    The analog signals are from another module which provides differential signals. The signals already have the required swing and VCM.
    Yes, I removed R67 and R65 as they would tie two of the inputs to ground. I also soldered R66 and R64, replaced C13, C66, SJP1 and SJP2 with 0ohm resistors. I also removed R25, R26, R60 and R71, replaced R5, R6, R11 and R12 with 49.9ohm reisistors according to the note on page 34 of the manual.
    I tried a continuous clock but the crosstalk is still there. I will find an attenuator to reduce the amplitude of the clock to see if it helps.
    Besides, I also tried to find out at what point the clock starts to have influence on the signal. I find out that as long as the clock is not connected to the ADC pin (removing SJP4 or SJP7 or C89/C90), the signal will be fine. Is it possible somehow the ADC is malfunctioning? We have been using this board like this for a while and I didn't notice this, so it might be a new problem.

    Regards,
    Lingmei
  • Lingmei,

    With the clock connected and running, if you remove R27 and R28, do you see the noise on CHA input? This would disconnect the ADC pins from the analog input. I am trying to see if the noise is getting on your signal through the ADC or the PCB via another way.

    Regards,

    Jim

  • Hi Jim,

    Thanks for your reply. I tried what you suggested and removed R27 and R28, the noise on CHA input is gone, and the noise on CHB is still there (signal from CHB is still connected to the ADC).

    I also tried to reduce the amplitude of the clock to the ADC by adding 3dB and 6dB attenuators, the noise is still there and its amplitude is not affected. 

    The outputs of the ADC are connected to a FPGA evaluation board (ML605) via a FMC-ADC adapter : 

    I notice that another output signal from one of the SMA connectors on ML605 board also has the noise, and the noise disappears if the clock to the ADC is disconnected or the ADC board is disconnected to the ML605 board.

    From what I see, I think it is less likely the problem of the board, more likely the ADC chip is generating something. What do you think?

    Regards,

    Lingmei

  • Lingmei,

    These are probably glitches from the sample and hold. They’re expected and careful input circuit design is needed to minimize ringing. This is the purpose of the series resistors (5Ω?) near the analog inputs or the R-C-R circuit used on our EVMs.

    Regards,

    Jim

  • Hi Jim,

    Thanks for your reply. The 5ohm resistors are soldered and the R-C-R circuit is used but the glitches are still there, so is there anything I can to do to reduce it? Also, does the glitches have an impact on the digitized data?

    Also, as I mentioned, the outputs of the ADC are connected to another board, and I have noticed that one output from the other board also has the noise, is this normal?

    Regards,

    Lingmei

  • Lingmei,

    The glitches could be kick back from the internal S/H. This is energy reflected back and the S/H should prevent most of it from passing through to minimize the affect on the digital output. If you are seeing it on the other board, is this board sharing any common power or GND connections?

    Regards,

    Jim 

  • Hi Jim,

    They share common ground.

    Lingmei

  • Hi Jim,

    I've just found out how the clock introduced crosstalk to the output from the FPGA board. There was another SMA connector used as an monitor to the output clock from the ADC, and it was quite close to the SMA clock which I observed the crosstalk. I removed that signal and the problem is solved now. Thanks for your help.

    I've got another question though. I just found out that the the quantification result from the ADC will occasionally give a wrong results (Figure attached).

    8713.ADC_Sine.tif

    I used the same clock (burst mode, 400+cycles) to sample a sinusoidal wave and I can often see a jump around the 380th sample. The are five curves in the figure, from 5 different measurements. Do you have any idea where this from? Thanks.

    Lingmei