ADS8866: ADS8866 analog input timing

Marc Schuman

Part Number: ADS8866

With the ADS8866, the acquisition phase is terminated with the rising edge of CONVST. My question is, is there any restriction on changes to the analog input signal after the CONVST rising edge? If there were a step change in the input during the conversion period, could that affect conversion results (indirectly, through coupled noise)? I have an external input multiplexer which I would like to switch during the conversion period, so that its output is stable before the ADC acquisition period begins with the falling edge of CONVST. Is that legitimate?

over 8 years ago

0 donald person over 8 years ago

Prodigy 10 points

Tacq - in this case 1200ns - from the timing diagram which shows how it is interleaved for the next reading with data clocked out.
Don't know your code or Op Mode but looking at datasheet figure 1 this implies a maximum SCLK of 12mhz for minimum Tacq..

0 Luis Chioye over 8 years ago

TI__Guru 55466 points

Hello Marc,

There are no restrictions on changes on the analog signal after the CONVST rising edge. During the conversion period, the sample and hold capacitor is disconnected from the external circuitry. The sampling capacitor will connect to the external circuitry at the beginning of the next acquisition period.

The sampling of the signal occurs at the end of acquisition. Provided that the sample-and-hold is completely charged to the target voltage at the end of acquisition within at least 1/2 LSB of the 16-bit resolution, there will be no degradation on the conversion results.

Below is a couple of TI designs that discusses ADC multiplexer applications. The change of channel occurs while the ADC is performing conversion, so the step has occurred prior the beginning of the next acquisition period. The SAR ADC driver circuit is optimized for settling after a full-scale step.

Please let me know if you have any questions,

Thank you and Best Regards,

Luis