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ADS131A04: synchronous slave mode timings

Part Number: ADS131A04
Other Parts Discussed in Thread: ADS8584S

Hi,
I'd like to use an ADS131A04 AD converter in a one-shot fashion, synchronous with a trigger event generated by a microcontroller.

If I'm not mistaken, I can use the ADC configured in synchronous slave mode, with DRDY pin connected to a micro controller GPIO pin (as explained in datasheet at section "10.1.3.3 All Devices Configured in Synchronous Slave Mode").
When I need a value I can toggle DRDY pin, and after waiting 3 complete conversion cycles the digital filter will provide a fully settled and valid data, that I can retrieve with SPI; after that when I need another value I can provide one more DRDY pulse (surely not synchronous with the previous one) to reset the filter and start a new conversion.
Is it right?

But here I need some important informations, that are missing in datasheet:
- which are the minimum DRDY "on-state" and "off-state" pulse width that I can feed?
- how can I know when new data is ready to be retrieved?
- the output buffer is overwritten when a new conversion is completed? even if I do not read the data from the SPI interface?

Many thanks,
Marco

  • Hello Marco,

    That is not quite how the device is intended to work. Synchronous slave mode is intended to be used when the host controls the device's master clock. In the scenario you are positing, your processor and the ADS131A04 would have to synchronized to the same clock so that the host could count the exact number of clocks before pulling DRDY from high to low for all three conversions required from when the digital filter is reset.

    I can answer your questions:

    • DRDY has to remain low during the entire frame. Typically the host will read continuously even before data is ready since it can monitor the status register. I don't know exactly what the minimum pulse width is, but I can find out for you if you'd like.
    • Refer to my comments above. Your processor has to have access to the ADS131A04 master clock so it can count how many clocks occur to send DRDY at the right time.
    • If the converter is on and running, the samples will still be generated.

    As you can see, the ADS131A04 was really designed for continuous conversion rather than on-demand conversion. This is typical for delta-sigma ADCs since they oversample the input and decimate. Have you considered using a simultaneous sampling SAR ADC like the ADS8584S? SAR ADCs are perfect for collecting data on demand.

    Regards,

    Brian Pisani

  • Many thanks for answering.
    I know this in not the typical use for delta-sigma ADCs, but the possibility to have a 24bits simultaneous sampling converter attracts me. So I'm evaluating if it can be used this way.

    - I would appreciate it if you could investigate the minimum t_on and t_off of a DRDY pulse.
    - Ok
    - Ok, the new samples will still be generated. But the output buffers will be overwritten with the new samples in any case or the buffers hold the old values if i don't read them each cycle? (like section "9.5.2.1.5 Data Ready (DRDY)" in asynchronous interrupt mode)
    - Anyway, how much time the output buffers update process lasts? (from when the output buffers start to update to the first DRDY falling edge)

    Best regards,
    Marco
  • Marco,

    - I would appreciate it if you could investigate the minimum t_on and t_off of a DRDY pulse. I will look into this.
    - Ok
    - Ok, the new samples will still be generated. But the output buffers will be overwritten with the new samples in any case or the buffers hold the old values if i don't read them each cycle? (like section "9.5.2.1.5 Data Ready (DRDY)" in asynchronous interrupt mode) The samples will always be overwritten with new data no matter what interface mode you use.
    - Anyway, how much time the output buffers update process lasts? (from when the output buffers start to update to the first DRDY falling edge) It should happen synchronously with DRDY.

  • Marco,

    In asynchronous interrupt mode, you should finish your communication with the device such that DRDY can transition high at least 0.5 mod clocks before the next time it is supposed to transition low. However if your communication routine is good, I think you probably will never run into this issue.

    In synchronous slave mode, it's my understanding that you should be able to keep DRDY high for the entire 3 samples you are waiting and then transition it low when you are supposed to start reading. However I want to caution you like I did before: synchronous slave mode requires synchronous operation between the host and the ADS131A04 i.e. the master clock you use for the ADS131A04 must be either generated by the host or the host must have some access to it. Without this then you will not be able to get synchronous slave mode to work.

    Brian

  • Hi Brian, thinking about your answers I have another question.

    The ADS131A04 datasheet at page 73 shows a typical application of 2 ADC configured in synchronous slave mode, sharing the same external clock, and a host MCU with the same or a different clock source (there is no explicit indication).

    Assuming that the MCU has access to master clock (or it's generated by itself).
    How can the MCU exactly know when to move synchronously the DRDY signal, since in the clock chain there are multiple clock dividers with a minimum value of 2?
    How the datasheet example can work?
  • Marco,

    If the host is the source of the clock, it can set up an internal timer to indicate when to assert DRDY. Nearly any embedded processing device will have some timer module which allows the MPU to be interrupted when some predetermined number of clock cycles.

    If it only receives the clock as an input, it will likely have to count the number of cycles, which is not very efficient. In general, synchronous slave mode is most useful with an FPGA or CPLD where the developer can create customer logic to handle the communication with the 131.

    Alternatively, asynchronous interrupt mode can be used easily with most microcontrollers. Daisy chaining is simplified since the first device in asynchronous interrupt mode will generate DRDY for the devices configured in synchronous slave mode.

    Regards,
    Brian