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HSMC-ADC-BRIDGE: Reference VHDL code for data aquisition from ADS5463 EVM + TI HSMC/ADC converter

Other Parts Discussed in Thread: ADS5463


I am trying to aquire data from the above configuration  using a Altera Arrow SoCKit. The schematic from both boards shows that they are compatible.(I think) 

1. is it possible to have a VHDL copy of the reference design using this bridge for any Altera board.

2. what is the purpose of this SPI bus. Am I supposed to configure this board using this port. If yes, how.

3. to read the data, all i have to do is read the data using the DCLK\HSMC_CLKIN2 ?

Thank you!

  • Hi,

    The purpose of the HSMC_ADC_BRIDGE card was to allow direct connection of many of our ADC EVMs into a variety of FPGA development platforms so that you could develop your design directly on your FPGA.    At the time the bridge card was designed a person from Altera actually chose the connector pins in the HSMC connector that we should route the various signals from the ADC to, taking into account things like getting the LVDS clock signal to a clock-capable IO and getting the data pairs to LVDS capable inputs.   We do not have example FPGA code to run on the FPGA platforms.   You would have to take into account the schematics for the ADC EVM together with the schematics for the bridge card to see which signals connect to which pins of the FPGA and develop your pin constraint file accordingly.

    The bridge card allows a wide variety of our high speed ADC EVMs to be connected to the Altera platforms, and many of these EVMs have a SPI port into the ADC to configure registers in the ADC.  The ADS5463 does not have any programmable registers inside the ADC and so no SPI port.  So the SPI signals through the bridge card would not go anywhere useful on the EVM.

    Once you trace through the signal paths to see how the LVDS clock and data signals connect up to the FPGA and you get your pin constraint file set accordingly, you would then use the clock signal from the ADC (named DRY for data ready) to latch the data into your FPGA in a DDR dual data rate fashion.  That is, both rising and falling edges of the clock signal are used to latch data from the ADC.  The Verilog code for our Altera-based TSW1400 capture card is available on the web site for the TSW1400EVM for reference.  

    One additional detail associated with the ADS5463 EVM is that the LVDS clock signal is *edge aligned* with the data bit transitions, what is commonly called source-synchronous clocking.   That means that there is *not* a valid window of setup and hold time for the data bits around the clock edges until you delay the clock signal by about 90 degrees.   After delaying the clock signal by about a quarter clock cycle then the clock edges would then be centered on the data bits and then you would have setup/hold time for the data around the clock edges.   Usually a PLL in the FPGA is used to delay the clock signal by 90 degrees before using it to latch the DDR data bits.


    Richard P.

  • Thank you very much for the informative feedback