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ADS8332: ADS8332 POR vs HW-Reset - device get's stuck.

Bertram Brummer
Intellectual 1556 points
Part Number: ADS8332

Hi, i have the issue that my device is somehow getting stuck  and assumption is that this is due to some  the device got into this condition a random drop of the supply voltage, violating the power up sequence.  The result is that the devices issues allways the same ADC value and even reprogramming does not change anything. In order to fix this I wonder whether a HW reset could solve this.  Since it is very difficult to reproduce this, at least the feedback that the HW-Reset will get the device in the same condition like the POR when power cycling the device. 

Could you please confirm?  Is there any other directions you woudl think about to address this with a high probability?

best regards, Bertram

  • 0
    TI__Mastermind 49465 points

    Hi Bertram,

    The ADS8332 requires that the analog supply (VA) is powered prior the digital supply (VBD).  In this device, the recommended operating conditions require that VBD does not exceed: (VBD < VA +0.2V).

    The power supply recommended sequence (p.44 datasheet) mentions that VBD should not exceed the analog supply voltage (VA).  If the analog and digital interface supplies for the ADC are not generated by a single voltage source, it is recommended to power on the analog supply and wait for it to reach its final value before turning on the digital interface supply.  In addition, the voltages applied to the analog input pins and digital inputs should not exceed the voltages on VA and VBD during the power-on sequence. It is best practice to issue a hardware RESET after power-up once both supplies are stable.

    In the bench, in the case where the recommended supply power-up sequence is not followed or in the case where communication becomes corrupted,  the device recovers after a hardware RESET without issue.

    You have mention that it is difficult to reproduce the issue in your system; however, if by chance you are able to capture an oscilloscope plot of VA, VBD when the drop in supply (capturing the timing/ramp rate and voltage levels of the brown out condition), we could attempt to reproduce and verify the RESET behavior on the bench.

    Thanks and Regards,

    Luis