DAC8801: Timing Diagram Incorrect

George Peterson

Part Number: DAC8801

Please confirm that Figure 19 in the February 2007 version of the datasheet has an error in the Timing Diagram. The truth table and note seem to imply that the last 14 bits that are clocked in will be latched into the DAC when CS goes high. This seems logical. The Timing Diagram shows an extra data bit and clock. This contradicts the Truth Table information.

over 7 years ago

0 Kevin Duke over 7 years ago

TI__Mastermind 46290 points

George,

It looks like the question has been asked / verified before:

https://e2e.ti.com/support/data_converters/precision_data_converters/int-precision_data_converters/f/75/p/68682/248565

I believe I would agree with Tony’s observations (looks like he also physically tested this) and what you have said based on the datasheet illustrations. The truth table remains correct in terms of describing the mechanics, only the timing diagram’s choice of illustration is certainly misleading as the labels of the individual bits suggest that the first 14 bits were actually the data latched. What is labeled “D13” would have been shifted out in this particular example.

Hope this helps.

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DAC8801: Timing Diagram Incorrect