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ADS1278EVM-PDK: Getting started with SPI Interface

Kory Olney
Prodigy 70 points

Part Number: ADS1278EVM-PDK
Other Parts Discussed in Thread: ADS1278, ADCPRO

Hello I am trying to interface my ADS1278 EVM-PDK with an NI myRIO using SPI. I am an ME and this is my first time trying to use SPI. I have a few questions to help me start pulling data off of the ADC. I have hooked up 8 analog devices to the board and have verified the signals through ADCPro. I have wired MOSI, MISO, and I am unsure with the CS and clock lines. If I want to use an external clock from my microcontroller at 4MHz I believe the CLK should be wired to J4.17. Do I need to wire anything to the SPI Clock or SCLK at J4.3, or j4.5 respectively or should they be left untouched? How do I decide on the CLKDIV settings? Also I am confused as to which pin I should run my chip select line to. I am only hooking up one slave device so I believe it can be held low at all time as I will have no need to switch to another device. I have switched s^ to SPI Format, but I am only getting zeros for my output to the microcontroller (as well as Oscope). What else do I need to do in order to initiate the transfer of data to the microcontroller?

Thanks so much for any help.

Kory

  • 0
    TI__Guru 68326 points

    Hi Kory,

    Lot of questions here, I'll try to answer them in order:

    Kory Olney said:
    If I want to use an external clock from my microcontroller at 4MHz I believe the CLK should be wired to J4.17. Do I need to wire anything to the SPI Clock or SCLK at J4.3, or j4.5 respectively or should they be left untouched?

    Yes - the CLK from your microcontroller can be provided to J4.17 (probe TP8 just to ensure the correct clock signal is present at the device pin). This clock controls the sampling rate in the ADC modulator (fMOD) as well as the digital circuitry. The SCLK, however, is your interface clock and is needed to shift data out of the device. Your microcontroller will need to provide this as well at J4.3 or TP6.

    Kory Olney said:
    How do I decide on the CLKDIV settings?

    The CLKDIV setting determines the ratio between the master clock input (CLK) and the modulator sampling rate (fMOD). The table below combines information from Tables 3, 6, and 8 in the ADS1278 datasheet to illustrate the relationship between these frequencies and the final output data rate:

    Mode[1:0]

    Mode Selection

    CLKDIV

    Max fCLK

    (MHz)

    fMOD

    Max fMOD

    (MHz)

    OSR

    fCLK/fDATA

    Max fDATA

    (SPS)

    0

    High-Speed

    1

    37

    fCLK/4

    9.25

    64

    256

    144,531

    1

    High-Resolution

    1

    27

    fCLK/4

    6.75

    128

    512

    52,734

    10

    Low-Power

    1

    0

    27

    13.5

    fCLK/8

    fCLK/4

    3.375

    64

    64

    512

    256

    52,734

    11

    Low-Speed

    1

    0

    27

    5.4

    fCLK/40

    fCLK/8

    0.675

    64

    64

    2,560

    512

    10,547

    Kory Olney said:
    Also I am confused as to which pin I should run my chip select line to.

    There is no chip-select pin on the ADS1278, so no need to worry about that.

    Once power and master CLK are present, you should see the data ready pin (/DRDY) toggle at the set data rate. This will indicate that the ADC is actively converting and ready to output new data.

    Hope this helps, let me know if you have further questions.

    Best Regards,