ADS5560: single-ended clock input

Hi,

it would depend on the rate of change of your clock frequency, or else it would depend on whether you could allow time for the clock to settle to a stable frequency after changing.   In general, if one of our data converters did not utilize a phase locked loop somewhere in the design then the clock frequency would be ok to change over time.   But if a device does include a phase locked loop or something similar in the design such as a delay locked loop, then the PLL or DLL would impose minimum and maximum operating limits as well as imposing a limit on how much the clock may be allowed to change over time.    The ADS5560 has a DDR (dual data rate) output that outputs sample bits on the rising and falling edges of the output clock, so the output clock must be close to 50/50 duty cycle even if the input clock is not close to 50/50 - and so there is a duty cycle correction circuit to hold the output clock to 50/50 based off of the sample clock and this is the main reason there *may* be an issue with the input clock changing frequency if it changes too rapidly.     At the low sample rates you are looking at you would need to set the SPI register bit called LOW SPEED to enable operation below 25Msps.   It may be that in low speed mode the duty cycle correction might be turned off - I would need to ask the design team about that. 

Regards,

Richard P.

thank you.

ADS5560 sample bits only on rising clock in our design,and sample clock frequency range is 12-24MHz, so ADS5560 work in low speed mode.

If ADS5560 include PLL or DLL, our design is unreasonable because PLL/DLL will take some time to lock clock.

The output clock is just delay some time（8.5-10.5ns）relative to the input clock, or the output clock is one of PLL/DLL output which input is the input clock?

if output clock is just delay some time（8.5-10.5ns）relative to the input clock,our design will be ok?

thank you.