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DAC3151: DAC delay Settling time above the specification

Part Number: DAC3151
Other Parts Discussed in Thread: DAC3174,

HI, 

Issue: we are seeing DAC delay of 1.2uSec compared to datasheet value of 11nsec. what is the Settling time with FIFO,SYNC,ALIGN disabled? 

Setup: fixed pattern sent to DAC input( CW tone with start bit is 0's) and monitored the DAC output in Oscilloscope. we are measuring directly at the DAC digital LSB input and DAC output, so our board timing is proper. 

DAC register settings, as below. FIFO disabled, SYNC Disabled, ALIGN Disabled( not required for our application).

Registers:
x0 x2404 \\ 2's complemement.
x1 x6C00
x2 x3FF0
x3 x0
x8 x0
x9 x0
xA xF0A0
x14 x0

Is this delay is not as expected in FIFO disabled mode, please suggest for the improvement or any register setting we need to do to improve.  

  • Hi,

    the latency through the device is in terms of DACCLK clock cycles, not ns.   The units in the datasheet are not correct for the digital latency, the digital latency is 26 clock cycles typical, not 26ns typical.  As we revise these datasheets we are getting some of these early typos out of the datasheets.  Take a look at the datasheet for the 2-channel version DAC3174 where we have corrected that unit from ns to DACCLK cycles.  We will fix this in the next DAC3151 datasheet as well. 

    What is the frequency of your DACCLK?   It looks like it is less than the max 500MHz if you are seeing a latency of about 1.2uS.   That typical latency is with the FIFO enabled, so it will be less than 26 clock cycles typical with the FIFO bypassed.    I don't know of any way to shorten the latency further other than to use a higher frequency for DACCLK to make the clock cycle shorter. 

    Regards,

    Richard P.

  • Hi Richard,

    Thanks for your quick response. Now it's clear, we are seeing 16/17 Clock cycle delay in our system.  DACCLK range is 5MHz to 160MHz in our application, currently we are measuring at 5MHz. 

    Thanks again for your support, it help to estimate our total system delay

    regards

    kumar.