Other Parts Discussed in Thread: DAC3174,
HI,
Issue: we are seeing DAC delay of 1.2uSec compared to datasheet value of 11nsec. what is the Settling time with FIFO,SYNC,ALIGN disabled?
Setup: fixed pattern sent to DAC input( CW tone with start bit is 0's) and monitored the DAC output in Oscilloscope. we are measuring directly at the DAC digital LSB input and DAC output, so our board timing is proper.
DAC register settings, as below. FIFO disabled, SYNC Disabled, ALIGN Disabled( not required for our application).
Registers:
x0 x2404 \\ 2's complemement.
x1 x6C00
x2 x3FF0
x3 x0
x8 x0
x9 x0
xA xF0A0
x14 x0
Is this delay is not as expected in FIFO disabled mode, please suggest for the improvement or any register setting we need to do to improve.