DAC3161EVM: DAC3161 EVM Interfacing with Artix7

Hi,

The DAC3164 uses a simple LVDS Dual Data Rate (DDR) interface which is nothing at all like a JESD204 interface.    you would need to develop an LVDS DDR interface from your FPGA to the DAC.   Xilinx has IO cell primitives specifically for this type of interface, namely the ODDR cell which stands for Output DDR.   You would need to connect the data streams for channel A and for channel B inside the FPGA to the ODDR cell such that the data for one channel outputs on rising edge of the ODDR output and the other channel outputs on the falling edge of the ODDR output.   We do not have example Xilinx code for the DAC LVDS Interfaces.

Regards,

Richard P.

Thank you so much for your reply. I have studied about LVDS. In that serializer and deserializer is there. Our design output is serial output. I have to give this serial output to DAC using LVDS.In my design Serializer is not needed right?

1. If Serializer is not needed I have to deserialize the signal alone?

2. After deserializing as u told i have to give it to channel A and channel B?

Hi,

I need to correct something I typed in my previous reply.   I said the DAC3164 uses a DDR interface where data is latched on rising and falling edges of the clock, which is true.  But I missed the part where you are using the single channel DAC3161 instead.  My apologies.   The 2-channel devices latches data for one channel on rising edge of clock and data for the other channel on falling.  In the 1-channel device, then only rising edge of clock is used.  Please see figure2 of the datasheet.   You would just need to provide 12 bits of LVDS data to the device, with a rising edge of the LVDS DATACLK.   There is no serialization of data for this DAC.  Just a parallel 12bit data bus plus clock.

Regards,

Richard P.

So Clock signal is connected to Pin No 1 (i.e)DACCLKP. and i have to give parallel datas to pin Nos 3, 5, 7, 9, 11, 13, 16, 19, 21, 23. Is that correct???? 

1. You mentioned its 12 bits of LVDS data bits. In the datasheet they have mentioned its 10 bits. Have you included DACCLKP and DACCLKN?

2. i ll be getting 10 bit serial data from previous designed block So In the programming side I have to convert Serial data to parallel to give the inputs to pin Nos 3, 5, 7, 9, 11, 13, 16, 19, 21, 23. Is that correct?

3. Other than this any need for programming for Interfacing Artix 7 with DAC 3161?

4. Can we directly connect DAC 3161and Artix 7 with adapter?

3. how much speed we can achieve using LVDS interface? because Arty 7 clk speed is 100MHZ.

Dear  Richard Prentice 

Thank you so much for your reply. Please reply for my previous question as soon as possible..

Hi,

you asked about the DAC3161 - that is a 12 bit DAC.  the pinout lists 12 data bits, and the timing diagram in Figure2 lists a data bus of 12 bits.  Regardless of the format of the data as you receive it, you will need to reformat the data into a form that conforms to Figure2 of the datasheet in order to present the data to the DAC.  You  will need to present the data on 12 LVDS pairs with setup time and hold time about the DATACLK.    There is flexibility in the setup and hold time however, as you may use the SPI registers to add delay inside the DAC to either the data or to the clock so as to make the setup and hold time of the DAC match up with what your FPGA is able to provide.

If your Artix7 is able to format the data to the DAC as shown in Figure 2, then the FPGA will be able to drive the DAC.  The DAC will not care what FPGA is the source of the data, just that the format and timing is acceptable.   If your FPGA is able to source a DATACLK of 100MHz with data in the right format, then you would be able to drive the DAC at 100Msps.      You mention adapter - what about an adapter? If you are planning to use the FPGA on a development board from the FPGA vendor and the DAC on our EVM, then you would need to *carefully* check the schematic pages of the DAC EVM and the schematic pages of the adapter EVM to see exactly what signals from the EVM match up with what signals into the FPGA development board and make sure that the development board is able to accept LVDS signals on those inputs and that the LVDS clock is going to a clock capable LVDS input on the FPGA.  We don't know anything about the development platform you would be using so you would have to check this yourself very carefully, or work with your FPGA vendor.

Regards,

Richard P.

Regards,

Richard P.