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ADS8344: SPI Protocol Question

Part Number: ADS8344


I'm debugging a problem and need a little help understanding the ADS8344 SPI bus.   Figure 4 (page 13 of the datasheet), indicates two things:

  1. DCLK must be low during the falling edge of the chip-select (CS#) event.    
  2. DCLK must remain low for a period of tCSS = 100ns before the first DCLK rising edge.

My application meets criteria 2, however, in some cases, criteria 1 is not met.    A falling edge of DCLK sometimes occurs 10-50ns after the falling edge of CS#.

What potential problems could there be in this case?


  • Hi Don,

    /CS low is used to initiate a conversion and bring the BUSY line low indicating that a conversion is taking place. As you have mentioned, when /CS is brought low to read back the conversion data, you have to wait a minimum delay of tcss (100ns) before the first DCLK rising edge.  As I understand things, if DCLK is not low while the falling /CS event, or if the 100ns delay is not met, problems aligning/capturing the conversion data or missing the MSB (Most Significant Bit) could occur.

    Thank you and Best Regards,