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AMC7823: Power-on reset and power supply sequencing for the AMC7823

Part Number: AMC7823

Hi,

I re-post this query as this has been unanswered on the forum:- Requested to please reply.

1)      With respect to BVdd being applied before Dvdd and AVdd, what is the expected failure in this condition? Is it resolved by a hardware or software reset?

2)      With respect to the assertion of the nSS pin during power up of the device, what is the expected failure in this condition? Is it resolved by a hardware or software reset? Is it resolved by doing an initial read of the DAC input shift register to clear the buffer? From page 36 in the AMC7823 data sheet Rev E.

I have the same doubt. I request for a reply on this.

Original Thread :- e2e.ti.com/.../88123

Regards.

  • 1- The BVDD has to be higher than AVDD and DVDD. It should not be a problem if BVDD applied first

    2- nSS should not be starting low. In case it is asserted low and the clock and data are running, the exchanged information between the master and slave could be wrong. We need to setup up the EVM in the lab for more spesific information 

  • Hi,

    Thanks for the reply.

    We are applying BVDD and DVDD together and then AVDD. All are of same voltage level - 3.3V

    I have attached an image of the circuit.

    Our nSS line is also connected to an FPGA. You may even comment on it.

    05_SUPERVISOERY _ PAGE1.pdf

    Regards.

  • The results of the series of power up/down test that Jojo had performed on the AMC7823 device, based on the customer's condition that has been provided below,  showed that the device does not get damaged without the power up/down sequence. But in the case where the BVDD is higher than the AVDD and DVDD during powerdown, a significant amount of current appears on BVDD. Though when AVDD and DVDD are returned to their normal levels (i.e. power up AVDD and DVDD back to 5V), the currents for all supplies go back to normal, particularly the BVDD current. During the course of the power up/down test, we have never seen any indications that a latch-up condition existed with the devices that were tested...

     

    Hence, the general concensus, Apps and test and characterization engineers, was that the device is not damaged by the abnormal power up/down sequence of event. But we cannot guarantee the correct functionality of the device if the device is exposed to the abnormal power up/down conditions. To ensure that the device will always operate normally, the correct power up/down sequence according to the datasheet must be followed