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DAC714: Sampling(Up-date) Rate times

cafain
Mastermind 6775 points

Part Number: DAC714

Hi,

Please let me ask basic questions.

From the information of ESP, the MSPS of DAC714 is described as 0.086MSPS.
Please tell me how to calculate this value.

※If what clock frequency is input to the CLK terminal will it be 0.086MSPS?

best regards

  • 0
    TI__Mastermind 46290 points

    Cafain,

    The Timing Specifications Table on page 4 of the datasheet indicates Data Clock Period minimum of 100ns, or a period of 10MHz. The interface needs 16-bits in order to transfer valid data and there is a 50ns setup time from the falling edge of A0 before clocks may be issued, so all together a valid frame would take 16*100ns + 50ns = 1650ns, or a period of about 600kHz. I'm not sure where the value you're referring to came from.

    From an analog perspective the device has settling time specified for various conditions, the best case being a 1 LSB step-size with 4us settling time, or period of 250kHz - so in the end the analog outputs will be the bottleneck for update rate as far as the output is concerned.