DAC8311: About the timing between SCLK and SYNCL

Masanori Tachibana

Part Number: DAC8311

Hello support team,

I have a question about DAC 8311.

Please teach me the specification regarding the timing from the falling edge of SCLK to the falling edge of SYNCL.
(Please refer to the figure below.)

I think this is t3 - t4. Is my understand right?
Or are there any other specifications?

Best regards,
M. Tachibana

over 7 years ago

0 Uttam Sahu over 7 years ago

TI__Genius 14220 points

Hi Masanori,

Thank you for your query. I am looking into your problem. Will get back soon.

Regards,
Uttam Sahu
Applications Engineer, Precision DACs

0 Uttam Sahu over 7 years ago in reply to Uttam Sahu

TI__Genius 14220 points

Hi Masanori,

From the timing diagram it comes out that there is no direct requirement of timing between the SCLK falling edge and /SYNC falling edge. However, if you observe there are few timing specs involved. Let's call the minimum time required between the SCLK falling edge and /SYNC falling edge as tx, then:
1. If the /SYNC rising edge is after the SCLK falling edge, the timing required is tx = t7 + t8, which essentially is t8 as t7-min is 0
2. If the /SYNC rising edge is before the SCLK falling edge, the timing required is tx = t8 - t10

I hope that answers your question.

Regards,
Uttam

0 Masanori Tachibana over 7 years ago in reply to Uttam Sahu

Genius 5350 points

Hello Uttam-san,

Thank you for teaching me.

I also thought about it.
I understood that falling edge of SYNCL must be earlier than that of SCLK.
What I want to know is the minimum time from the falling edge of SYNCL to that of SCLK.
I guess that it is t2 + t4. Since minimum value of t4 is 0 ns, it's t2.
Is this correct?

Best regards,
M. Tachibana

0 Uttam Sahu over 7 years ago in reply to Masanori Tachibana

TI__Genius 14220 points

Hi Masanori-san,

You are right that for the start of the sequence where the /SYNC falling edge is before the SCLK falling edge, the minimum timing requirement between the two is t4 + t2. As t4-min = 0, it is effectively t2. However, as t2 is the minumim SCLK on-time, this requirement is actually redundant and hence, not specified.

Regards,
Uttam

0 Masanori Tachibana over 7 years ago in reply to Uttam Sahu

Genius 5350 points

Hello Uttam-san,

Thank you for teaching me.

I understood.
Your advice was very helpful.

Best regards,
M. Tachibana

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DAC8311: About the timing between SCLK and SYNCL