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ADS54J42: ADS54J42 setup question?

HENRY JUNG
Expert 2030 points
Part Number: ADS54J42


Dears.

We are considering developing the ADS54J42.
We are using JESD204B for the first time.

We set it as follows.
Sampling uses 276.48Mhz
Bandwidth is 120M.
Serdes uses four lines.
LMFS is 4211.
No decimation.

What is the input-clock and Sys-ref clock value of the ADS54J42?


I would like help with setting values.

Thank you.

  • 0
    TI__Guru* 91947 points

    Henry,

    The device clock will be 276.48MHz. Max SYSREF = device clk / K. In the example I am sending, K = 32, so the maximum frequency for SYSREF is 8.64MHz. This value though can be divided down by any integer and still work, which allows you to operate with a much slower SYSREF clock, which helps remove harmonics caused by this clock. Once your JESD204B link is established, SYSREF can be disabled, which is what most users do. I have attached register settings you can use for your setup. If you go to the JESD204B page on the TI website, you will find many articles, app notes, blogs, and videos that will help you come up to speed quickly with understanding this standard.

    Regards,

    Jim

      ADS54J42_LMF_4211_reg_map.cfg