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DAC5682Z: FIFO error not getting cleared

Part Number: DAC5682Z

Hello,

I am using a FMC204 with DAC5682z in my project. I have interfaced it with Virtex-7 FPGA board. I am generating a clock from the FMC chip and feeding it to MMCM to generate the CLK (250 MHz DDR) and CLKDIV (125MHz) for OSERDES. I use OSERDES to generate Data, Sync and DCLK.  I am trying to generate a 1MHz square wave on FPGA based on CLKDIV using counters.  Output pattern is xAAAA and x5555.

I configure the AD9517 chip on FMC through a microblaze SPI which would generate the CLKIN(500MHz) and also sends ref. Clk to FPGA. Then I do the following steps for DAC configuration:

  1. Reset DAC by configuring CPLD of FMC.
  2. Set DLL_Restart bit (Config 8)
  3. Config1 = x10 or x00 (Even tried various FIFO_offset configs)
  4. Config2 = xC0 or x80.
  5. Config3 = x40
  6. Status4 = x00
  7. Config5 = x02. (PLL_Bypass)
  8. Config6 = x0E (PLL_Sleep)
  9. Config7 = xFF.
  10. Config9 = x00.
  11. Config10 = xC8 (According to datasheet)
  12. Config11 – Config15 = x00.
  13. Send a signal to FPGA from Microblaze to generate DCLK. Sync and Data is not yet enabled.
  14. Check the status registers. (Fifo_Error is already present)
  15. Restart DLL (Config 8). DLL Lock is verified from Status0 read.
  16. Send a signal to FPGA to enable Data and Sync signal flow simultaneously.
  17. Keep monitoring Status0 and Status4 in microblaze. (Clear to x00 and read after a delay)

 

After following this procedure, I could see the FIFO_err bit is always set and I am not able to come out of the error. I have tried with various modes of Dual DAC and single DAC. Only in Single DAC mode with FIR disabled and SW sync, the Status4 returns 0. But the waveform would still be not the expected square wave.

 I would be really glad if you could provide some help regarding this.

 

Thanks in advance,

Abhijith

  • Hello,

    Can you please comment on the possible reasons of the FIFO_ERROR or any ways to debug and fix it?

    Thanks and Regards,
    Abhijith
  • Hi Abhijith,

    Once you have setup everything can try to set config 3 bit0 to 1 and toggle config3 bit 1 to 1 and see if you are able to set anything out of it. Also the output is going through a transformer and which act kind of like a band pass filter as a result your square wave might looks distorted.

    Regards,

    Neeraj Gill

  • Thanks for the reply.

    Yes. I tried using the SW sync also before. Only in the 1x1 mode, I do not get a FIFO error. What I am not able to understand is that the ouput waveform still remains same as when the FIFO error was present.

    I wanted to change my method and use the following procedure. Could you tell me if the following procedure is fine for making the DAC work.

    1. Provide CLKIN
    2. Config all registers.
    3. DLL restart and wait for DLL lock
    4. Enable sending data to DAC from FPGA.
    5. wait for sometime.
    6. Enable SYNC for data transmission.

    Is it necessary to send data and sync signal at same time or can we wait for a random amount of time before enabling 'sync' after data. Would this lead to FIFO error?`

    Thanks and Regards,
    Abhijith