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ADS7950-Q1: The impact on source impedance accuracy

Part Number: ADS7950-Q1

Hi team,

Our customer is considering to use 4ch ADC over 10bits resolution.

In the datasheet, it is written that if the source impedance is large, it deteriorates accuracy.

Their use case, in the worst case, the source impedance becomes 50 kΩ or more.

Is there any data or theoretical value indicating the influence when the source impedance is between 50 kΩ and 100 kΩ?

I am glad if there are data whose horizontal axis is up to 100 kΩ in Figures 59 and 60.

Could you tell us the formula that indicates the time it takes for the microcomputer to instruct the A/D conversion of 4ch to receive the result?

Best regards,

Tomoaki Yoshida

  • Tomoaki San

    As of now we do not have test results for ADC performance with input source impedance more than 50k Ohm.

    some of the ways to address performance degradation caused due to higher input source impedance are

    1. Reducing sampling speed of ADC

    Can you please let me know what is the sampling speed customer would like to operate this device. If sampling speed is much lower <100ksps then performance degradation is comparatively lower compared to higher sampling speeds.

    2. Adding buffer amplifier between MXO and AINP pins

    Please refer to section 9.2.2 which explains how adding a buffer amplifier between MXO and AINP can help with settling issues. You can suggest customer to implement similar architecture in his design

    If you can let me know what is the sampling speed at which customer operating this device, maximum input signal swing, exact input imedance value then I can help you with suitable op-amp that can be used between MXO and AINP pins.

    Figure 47 highlights the timing diagram for 10 bit device. This can be used to calculate time for one ADC conversion cycle. You need to know what is the clock frequency used in this case

    Thanks & Regards

    Abhijeet 

  • Hi Abhjieet-san,

    Thank you for quick response.

    The sampling rate they target is around 100 KSPS and it can not be reduced below this level.
    The maximum input amplitude is supposed to be 5Vpp as it intends to match the input full scale of the ADC.
    The upper limit of the impedance assumed at the moment is 60 kΩ.

    They are also considering to relax about the execution resolution, so I'd like to determine if this device can be used depending on how the accuracy deteriorates with a source impedance of 60 kΩ.

    When reading data of one channel, sampling is performed in the first frame as shown in Figure. 45, conversion and output are performed in the second frame.
    That is, it takes two frames from the falling edge of CS until end of reading data.
    Is this recognition correct?

    Best regards,
    Tomoaki Yoshida
  • Hi Abhjieet-san,

    I have additional request.
    I found an article at the URL below.
    e2e.ti.com/.../using-sar-adc-tina-models-much-ado-about-settling

    I think that we can estimate accuracy or settling time by simulation like Fig.2.
    Could you tell me the equivalent circuit of the ADS7950-Q1?
    I think that it is good to know the constant values about the sampling capacitor and the Ron the switch.

    Best regards,
    Tomoaki Yoshida
  • Tomoaki San

    Figure 50 of ADS7950-Q1 datasheet gives MUX and ADC input equivalent circuit. MUX Ron is 200 Ohms. ADC sampling switch resistance is 80 ohms. For ADC sampling capacitor value is 15pF as mentioned in Applications section 

    If you need more detailed theory on input settling analysis of SAR ADCs , please refer to SAR ADC precision lab videos

    Please let me know if you need additional information

    Thanks & Regards

    Abhijeet