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ADC12J4000: ADC12J4000EVM Test Pattern mode

Shai Gilboa
Prodigy 60 points
Part Number: ADC12J4000

We are evaluating the ADC12J4000 ADC using both the ADC12J4000EVM and the TSW14J56EVM.
The TSW14J56EVM is running with its original firmware.
Spectral display (FFT) looks fine when injecting RF carrier signal.
However, result looks improper when switching to an internal Pattern signal (Ramp).
Attached is a picture of the Pattern in time domain as captured by the HSDC Software.


 As can be seen, ADC12J4000_Bypass is selected.
“Ramp Test” mode is selected in the ADC12J4000EVM GUI.
Test pattern is enabled in the TSW14J56EVM GUI.
We followed the instructions as in SLAU551B (ADC12J4000EVM User's Guide) and no errors are reported by either GUI applications.
Please advice regarding the issue described above.
Is there anything that we overlooked which could explain this result?

Regards,

  • 0
    TI__Mastermind 43910 points

    Hello Shai

    The ramp test patterns are always a ramp in the octet data for each JESD204B lane. Since the DDC bypass mode uses 12bit values which span octets it will not give a smooth ramp in the 12 bit data. he pattern you are seeing is the expected result of processing the octet ramp information as 12 bit samples.

    An alternative test pattern you can use is the ADC test pattern. This test pattern is created at the output of the ADC logic block and does contain a repeating set of 12 bit data values which are useful. Please refer to section 7.4.5.1 ADC Test-Pattern Mode and Table 33 for the pattern information. This pattern is enabled by setting Bit 2 of Register 0x058h. (ADC_PAT_EN).

    I hope this is helpful.

    Best regards,

    Jim B

  • 0 in reply to Jim Brinkhurst1
    Prodigy 60 points

    Hello Jim,

    Thank you for this response, which was helpful!

    It looks like that the ADC Test Pattern is captured successfully.
    It has a period of 16 samples.
    Attached is a Excel file with the captured data, as generated by the HSDC SW.


    TestPatt.xlsx

    Best Regards,