ADS54J54: Unable to send data via JESD204B

Hi,

is this a design that is completely on hardware of your own design or are you using our EVM into your FPGA card?  Which Xilinx FPGA please?

The ADS54J54 EVm works into our Altera-based TSW14J56 capture card as well as our Altera-based TSW14J50 capture card using the default ADC and clock chip configuration that comes with the ADC SPI GUI, and the the HSDCPro ini file for the respective capture cards.    There *is* an issue with the current HSDCPro capture card GUI for this particular EVM that will be fixed with the next revision of HSDCPro.   The ADS54J54 requires *two* LVDS SYNC signals from the FPGA and the default HSDCPro firmware for the Altera devices on our capture cards do not enable the second SYNC signal.  We have firmware that fixes this, but this will not be an issue for your Xilinx setup.    You will need to have your Xilinx FPGA firmware drive both SYNC signals, however.   There  is a SYNC for channels A and B, and another for channels C and D.

We also have our ADS54J54 EVM working into three different Xilinx FPGA development boards.  We work with the Xilinx VC707 development platform by way of our TSW14J10 capture card.   We work with the ZC706 development platform through the TSW14J10 capture card I think but the ini files for that setup are not in the current HSDCPro.   and we work with the KC705 development platform directly but only on channels A and B because that FPGA board only has four lanes of JESD through the FM connector. 

So this ADC does work with Xilinx JESD204b IP when using our EVM and the config files that come with the EVM SPI GUI.   For older Xilinx IP we do have to enable a second clock from the LMK04828 clock chip back through the FMC connector to the FPGA.   The older Xilinx IP wanted two clocks, I am told that newer Xilinx IP only needs one clock, and the default EVM config files only set up one clock.

But those are the only two issues I tend to run into with ADC to FPGA bring-up; the fact that the ADC needs two SYNC signals and the Xilinx IP might require two clocks. 

May we see the configuration of the ADC SPI registers that you are using?  And the type of FPGA you are using?  We need to know a lot more about what you are doing before we could say what is wrong unless it is one of the two simple things mentioned above.

Regards,

Richard P.

Hi Richard,

Thanks for your timely reply.

Yes, this ia a design that is completely on our own hardware.

We using 7K410T and config Ads54j54 through FPGA.The configuration follows the description of the initialization sequence in the section 7.3.12 . We just change the register 0x0c to use all SYSREF pulses and the register 0x1d to generate test pattern:
0x0d -> 0000
0x0d -> 0202
0x0d -> 0303
0x0c -> 0009
0x1d -> 0060
0x0d -> 0202
0x0d -> 0303
wait for two SYSREF pulses
0x0d -> 0101

As you mentioned, I have noticed that xilinx ip core requires 2 clocks, and also connects two sets of SYNCB signals to ADS54J54. Because the same LMFS configuration is used for all four channels, the SYNCbAB and SYNCbCD are drived with the same signal in the FPGA 

Is there any reason why ADS54J54 may only send BCBC without sending data?

Regars,

Ray Xie