• State TI Thinks Resolved
  • Locked Locked
  • Replies 6 replies
  • Answers 3 answers
  • Subscribers 46 subscribers
  • Views 1379 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADS7841-Q1: Difference from normal operation

na na78
Guru 16770 points
Part Number: ADS7841-Q1
Other Parts Discussed in Thread: ADS7841

Hi

The following waveform is obtained by customer.

Could you please check it and tell us your view?

① You can see glitch on DIN.  It should be generated by host.

 It doesn’t cross DCLK rising edge so it seems not to be latched.

However, it should be avoided as long as possible, right?

②　DIN has been kept high before the first control bit is sent.

Does it have impact for device operation?

③ As you can see DOUT the device outputs high while control bits are sent.
Does it malfunction?

Do you have any advice?

BestRegards

  • 0
    TI__Mastermind 21685 points
    Hello na na78,
    I will review and come back to you on this.
    Thanks,
    Vishy
  • 0 in reply to Vishy Viswanathan
    TI__Mastermind 21685 points

    Hello,

    >>>However, it should be avoided as long as possible, right?

    Yes, the glitch at the end of ADS7841 DIN control byte should be avoided so device doesn't misinterpret the command.

    >>>DIN has been kept high before the first control bit is sent. Does it have impact for device operation?

    Yes, ADS7841 device requires the first bit (Start bit) of the control byte to be set high.

    >>>As you can see DOUT the device outputs high while control bits are sent. Does it malfunction?

    Looks to me customer is using the device in 16 clock cycles per conversion mode. In this mode, control byte for conversion n+1 is overlapped with DOUT data of conversion n. Please see Figure 4 from data sheet below

    As you can see above DOUT4 to DOUT0 of conversion n are overlapped with control bits of conversion n+1.

    I tested this 16-bit conversion on a bench board and enclose below the logic analyzer capture. Device is converting channel 3 in single ended always powered mode (control byte = 0xE7).

    Thanks,

    Vishy

  • 0 in reply to Vishy Viswanathan
    Guru 16770 points

    Hi Vishy

    Thank you for your reply.

    >Yes, the glitch at the end of ADS7841 DIN control byte should be

    >avoided so device doesn't misinterpret the command.

    According to the customer, the glitch seen on DIN is not latched by rising edge of DCLK.

    If this glitch would never been latched by rising edge of DCLK, could it be "Don't care"?

    It's OK if I can hear just your view about it.

    I explain that the guideline is just to avoid such glitch but the glitch might not be avoided in their system.

     

     

    >Yes, ADS7841 device requires the first bit (Start bit) of the control byte to be set high.

    I want to confirm the following.

    DIN is held high other than during sending control byte but that can be accepted.  Is my understanding correct?

     

    >As you can see above DOUT4 to DOUT0 of conversion n are overlapped with control bits of conversion n+1.

    The phenomenon shown in question 3 is representing the blue circled point in the following figure.


    That means DOUT is overlapped with first control bits.

    Is it unexpected behavior?

    Do you have any advice?

     

    BestRegards

  • 0 in reply to na na78
    TI__Mastermind 21685 points
    >>>>According to the customer, the glitch seen on DIN is not latched by rising edge of DCLK. If this glitch would never been latched by rising edge of DCLK, could it be "Don't care"?

    According to DS, when CS\ is low, DIN is latched on rising edge of DCLK. Most likely this glitch gets ignored by the device. Still I would suggest glitch proof is something customer needs to test and ensure for the desired clock frequency of the device and over operating conditions.

    >>>>DIN is held high other than during sending control byte but that can be accepted. Is my understanding correct?

    Yes, DIN held high other than during control byte should be fine. I have not exercised this condition on the bench but think this should work as device samples DIN only during CS\ is low for reading the control byte.

    >>>>That means DOUT is overlapped with first control bits. Is it unexpected behavior?


    No. This is normal and expected behavior.

    Thanks,
    Vishy
  • 0 in reply to Vishy Viswanathan
    Guru 16770 points
    Hi Vishy

    I could make it clear for first two questions, thanks!


    Regarding to last question I want to confirm.

    >>That means DOUT is overlapped with first control bits. Is it unexpected behavior?
    >No. This is normal and expected behavior.
    For example, that means it is possible that DOUT would be outputted after idle term (S, A2, A1, A0, MODE) is latched. Is it correct?
    In the customer system, the first DOUT is varied at the end of idle.


    If possible, could you tell me when the first DOUT is outputted?


    BestRegards
  • 0 in reply to na na78
    TI__Mastermind 21685 points

    >>>>>If possible, could you tell me when the first DOUT is outputted?

    According to DS, DOUT is enabled within 70ns of CS\ falling (Table 7). On the bench I can see DOUT active immediately as well.   While control byte for next conversion is set, DOUT bits of any previous conversion is getting shifted out.

    Please see a logic analyzer capture below with my ADS7841 test setup. CSB is asserted and DIN sent is 0x97 corresponding to selecting single ended conversion on channel 0. Some remaining DOUT (0x87) of previous state is shifted out when DIN = 0x97 is sampled by device.

    Thanks,

    Vishy