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DAC5682Z: Problem with running DAC5682Z at sampling rates higher than 250MSps

Arpit
Prodigy 20 points
Part Number: DAC5682Z
Other Parts Discussed in Thread: CDCE72010,

Hi,

We have DAC5682Z  DAC on FMC interfaced to Virtex 6 FPGA and CDCE72010 for input clock. I have been using it at 250 MSps for generating waveforms without any problem for a few years. But when I tried higher sampling rates I got some bizarre results. I conducted tests at 500 MSps and 1 GSps and here is what I observed:

Main Clock(MHz)

 Data Clock(MHz) Data Waveform*(MHz) DAC Output(MHz) Expected DAC output(MHz)
250 125 125 125 125
500 250 250 125 250
500 250 125 62.5 125
1000 500 500 166.667 500



*data waveform is alternating extremes.

I have turned off interpolation filters and PLL and am setting config 10 for DLL as per table 7.7 in data sheet. I am also sending appropriate sync event after every 125M cycles,

I thing I am missing something very trivial that is resulting in these weird factors of 2 and 3, and would appreciate any help in resolving this.

Thanks in Advance.

Regards,
Arpit.

  • 0
    TI__Mastermind 20541 points
    Hi Arpit,

    I am looking at your question. I will get back to you as soon as I can. In meantime can you please send me output plots for all the results you are seeing.

    Regards,
    Neeraj
  • 0 in reply to Neeraj Gill
    Prodigy 20 points

    Hi Neeraj,

    Here are some frequency combinations that I tried:

     

    CLK - 1000 MHz     DCLK - 500 MHz     Data - 500 MHz     Output - 166.667 MHz


     

     


    CLK - 1000 MHz     DCLK - 500 MHz     Data - 250 MHz     Output - 83.333 MHz


     

     


    CLK - 500 MHz     DCLK - 250 MHz     Data - 250 MHz     Output - 125 MHz

     

     

     


    CLK - 500 MHz     DCLK - 250 MHz     Data - 125 MHz     Output - 62.5 MHz

     

     

     


    CLK - 250 MHz     DCLK - 125 MHz     Data - 125 MHz     Output - 125 MHz

     

     

    Regards,
    Arpit.

  • 0 in reply to Arpit
    TI__Mastermind 20541 points

    Hi Arpit,

    Can you please specify which mode you are using your DAC in?

    There is table 8 in DAC5682z datasheet which specifies the modes of operations available.

    Also when you change DCLKP/N frequency, you will also have to update the DLL settings according to table below.

    Regards,
    Neeraj Gill