• State TI Thinks Resolved
  • Locked Locked
  • Replies 6 replies
  • Answers 2 answers
  • Subscribers 47 subscribers
  • Views 902 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADC08D500: problem while using for delay time measurement

Shawn Ding
Expert 3190 points
Part Number: ADC08D500

There is a problem while using ADC08D500 to sample a analog signal. Set DES mode as the operation mode and 1Gsps sample rate, and use FPGA to get the ADC data. the circuit was used to measure the signal delay.

The ADC output clock is 250MHz and connect to FPGA. Using FPGA internal PLL to delay the clock phase 0,90,180,270 degree and get four clocks, and these clocks are supplied for the counters. finally , add the four counter 's value as the result of delay time.

while given 100ns delay, the measuring result is 90ns,

given 200ns delay, the measuring result is 200ns

given 300ns delay, the measuring result is 305ns

So please help to analyze the reasons, Thanks a lot !

  • 0
    TI__Mastermind 44680 points

    Hi Shawn

    I don't think I fully understand how you are processing the ADC data, and what you are measuring to determine the 'delay' value.

    The ADC will output data on 4 data buses. The single DCLK output is used to capture this data into the FPGA. With a 500 MHz input clock, the sample rate in DES mode is 1 GSPS. The 4 output data buses update at 250MSPS, so 4 new data values are captured into the FPGA every 4ns. In 100 ns there will be 100/4 = 25 groups of 4 samples output.

    Could the apparent error in your delay measurements be related to the fact that the samples are captured into the FPGA in groups of 4?

    Please provide more details on exactly how the ADC is behaving differently than you expect. It might be useful to provide a text file containing the data from the ADC. If you can organize the data in 4 columns, so the values from DQd, DId, DQ, DI are in each column that is usually the easiest to analyze.

    Best regards,

    Jim B

  • 0 in reply to Jim Brinkhurst1
    Prodigy 30 points

    I use two pulse signals to test,one of which is used to start the counter and the other is input to ADC(ADC08D500). When ADC output the max value of the pulse that is input the ADC,the counter output a value. The value is 'delay' value between two signals. And the interval between two pulses can be adjusted. Adjust the interval between different two pulses so that the counter gets different values.

  • 0 in reply to user4401406
    TI__Mastermind 44680 points
    Hi Shawn
    Thanks for the additional detail.
    So you are stopping the counter when the group of 4 samples received from the ADC includes the peak value of the analog pulse waveform. Depending on which of these 4 samples contains the max value, the counter result needs to be offset by some amount. Every 4 ns your FPGA receives 4 samples captured at 1 GSPS. Therefore the sample with the peak can be captured at 0, 1, 2 or 3 ns offset. Are you including that offset in your counter total algorithm?
    Best regards,
    Jim B
  • 0 in reply to Jim Brinkhurst1
    Prodigy 30 points
    Hi, Jim B
    I use chip ADC08D500 to sample signal, and set DES mode as the operation mode and 1Gsps sample rate. I use the output clock of chip ADC08D500 whose frequenc is 250MHz to input a IP core of PLL(phase locked loop) which output frequence 50MHz. Then, I use an oscilloscope to measure 50MHz. However, The oscilloscope measured at about 51MHz clock fluctuations, is not critical 50MHz. This phenomenon shows that the output clock of chip ADC08D500 is not accurate. Why? Is there a problem with the chip calibration?
  • 0 in reply to user4401406
    TI__Mastermind 44680 points

    Hi

    What is the amplitude of the CLK+/CLK- differential clock signal applied to the ADC08D500? Does it meet the requirements listed in the CLOCK INPUT CHARACTERISTICS section of the Converter Electrical Characteristics table on page 11 of the datasheet?

    Is the CLK+/- signal AC-coupled to the ADC as required for proper common mode?

    Is the ADC power supply within rated tolerances?

    Can you share the schematic showing all ADC connections?

    The output DCLK is simply CLK/2, so it will only be inaccurate if the input clock is not correct or the ADC is not properly powered or configured. The DCLK output is not dependent on the ADC calibration process, except that while calibration is occurring the output DCLK is muted.

    Best regards,

    Jim B

  • 0 in reply to Jim Brinkhurst1
    TI__Mastermind 44680 points
    Hi
    There is one other consideration when using the ADC08D500 in DES mode.
    The calibration process should not be initiated when the device is in DES mode. First the mode should be changed to non-DES mode, the calibration should be initiated, and after calibration finishes then the device can be returned to DES mode.
    See the On-Command Calibration section of the ADC08D500 datasheet.
    Best regards,
    Jim B