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ADS5463: Parallel LVDS

Amir shahi
Prodigy 240 points
Part Number: ADS5463
Other Parts Discussed in Thread: TIDA-00069

Hi,

we want to connect ADS5463 (12bit,500Msps and parallel LVDS Output) to Xilinx SOC chip, but I don't have idea about parallel LVDS.

1) I find and read some thing about serial LVDS but I could not find good document about parallel LVDS? and

2) How can I connect this parallel LVDS to FPGA pins?

3) How can I read my data from parallel LVDS?

4) how dose data transfer with standard?

5) and what is the difference between serial LVDS and parallel LVDS?

6) I think you have a Verilog code for parallel LVDS for the TSW1400EVM, please send this code for me as a reference.

  • 0
    TI__Mastermind 44550 points

    Hi Amir

    Depending on the relative frequency of the ADC sampling clock and the capabilities of LVDS, either serial or parallel LVDS interfaces are possible.

    For a lower sample rate ADC it is possible to use a serial interface, where multiple data bits are sent on a single data pair during one ADC input and/or link frame clock cycle. As ADC clock frequencies go beyond a few hundred MHz it is no longer possible to send many bits per clock in a single pair. In those cases a parallel interface is more practical. In these interfaces the multiple bits are transmitted on multiple data pairs, to keep the data rate within the limits of LVDS capabilities.

    Here is a good example of ADC to FPGA firmware for a parallel LVDS interface.

    http://www.ti.com/tool/TIDA-00069

    Best regards,

    Jim B

  • 0 in reply to Jim Brinkhurst1
    Prodigy 240 points

    Thanks Jim,

    Jim, my first problem is the operation of parallel LVDS, I understand serial LVDS. but I am confused about parallel LVDS. I have Idea but I don't Know is it trou or no. for example we have a ADC with 12 bit resulotion and 500Msps and 12 pair parallel LVDS outputs, this mean that in every clock we have a complete 12 bit from sample N on 12 pair parallel output?

    Thanks again,

    Amir

  • 0 in reply to Jim Brinkhurst1
    Prodigy 240 points
    Jim, my first problem is the operation of parallel LVDS, I understand serial LVDS. but I am confused about parallel LVDS. I have Idea but I don't Know is it trou or no. for example we have a ADC with 12 bit resulotion and 500Msps and 12 pair parallel LVDS outputs, this mean that in every clock we have a complete 12 bit from sample N on 12 pair parallel output?
  • 0 in reply to Amir shahi
    TI__Mastermind 44550 points

    Hi Amir

    Your idea is correct.

    Please refer to the ADS5463 datasheet.

    The PIN CONFIGURATION diagram on page 11 and the Table 1. PIN FUNCTIONS information on page 12 show the 12 LVDS pairs (D0 to D11) that output the ADC data. Figure 1.

    Timing Diagram on page 9 shows the relative timing for CLK input, DRY, Dn and OVR output LVDS pairs. The 12 data bits and OVR overrange LVDS pair update once per input CLK cycle, presenting the full 12 bit code of the ADC simultaneously, along with a bit indicating whether the signal is inside or beyond the full scale range of the converter.

    For a 500 MHz input CLK, the output Dn and OVR values update at 500 Mbits/sec. The DRY (data ready) output is essentially an output clock that will be used by the FPGA to strobe in the data using DDR (dual data rate) clocking. If CLK is 500 MHz, the DRY signal will be 250 MHz. The Dn and OVR values update on both rising and falling edges of DRY.

    I hope this is helpful.

    Best regards,

    Jim B

  • 0 in reply to Jim Brinkhurst1
    Prodigy 240 points
    Thanks Jim for your help,
    but I can not download the test data part in this link

    www.ti.com/.../TIDA-00069

    I don't know what's the problem?
    if you have Verilog cods please send that code for me as a reference, it may help me more.

    Regards,
    Amir
  • 0 in reply to Amir shahi
    TI__Mastermind 44550 points

    Hi Amir

    I'm not sure why that other link is broken. I'll try to get it fixed. You should be able to access the test data document here:

    http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=slaa545&fileType=pdf

    The only code I'm aware of is available in the More literature section at the bottom of the TIDA-00069 folder. It is listed as TIDA-00069 Firmware. Here is a direct link: http://www.ti.com/lit/zip/tidc202

    The .zip file contains a .qar file that can be opened using the Altera Quartus design tool.

    Best regards,

    Jim B

  • 0 in reply to Jim Brinkhurst1
    Prodigy 240 points
    Thank you very much Jim,