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ADC3222: ADC3222

Shlomi Yehezkia
Mastermind 6150 points
Part Number: ADC3222

Hi,

 

I am using ADC3222 in my receiver design and I encountered a problem:

The input signal is a baseband signal (I/Q data) with symbol rate of 400 kHz and the sampling clock frequency is 21 MHz

I have performed few tests and it looks that the noise floor of the sampler is high:

1)      Using a CW signal at 10 ÷  80 kHz at -24 dBm and SNR bigger than 25 dB I get  SNR of ~10 dB (the SNR encountered at 10 kHz and 80 kHz is the same, so it did not look like a sampling clock jitter problem).

2)      Grounding the I/Q input pins of the components I see ~5 digital bits changing with time.

3)      Using a CW signal with SNR of 6 dB  at -4 dBm  dB I get  SNR of ~6 dB

I will appreciate if you can help improving my design.

Thanks,

Shlomi

  • 0
    TI__Intellectual 785 points
    Hi Shlomi,
    1. Please provide the raw time domain data file of your capture with exact sampling rate and input frequency.
    2. Please put device in RAMP test pattern mode. You should be able to see digital code changing once in 4 clock and following a ramp pattern from 0 to 4095. This is to ensure that digital link between ADC and FPGA(or ASIC) is correctly working.
    Regards,
    Sourabh