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ADC08200: Spikes in ADC08200 Digital Output Data

Raghavendra Mendon
Prodigy 110 points
Part Number: ADC08200
Other Parts Discussed in Thread: LMH6702

Hi All,

We are using ADC08200 for sampling pulse signal ( pulse repetitive interval= 1uS, pulse width = 200nS, pulse voltage level: 300mV to 2.5V). We are seeing spikes in output, when we plot in Chipscope (xilinx ISE). We are observing spike even when apply DC signal to ADC input. As per earlier suggestion from TI to add buffer between ADC output and FPGA, spikes not reduced with buffer. Also added 50ohm resistor at input, still spike not reduced. Kindly request to suggest, what could be issue due to which spike observed at the output of ADC.ADC08200_Schematic_Spike_issue.pdf  

LPF part LT6600 added in front of ADC along with voltage follower using LMH6702, but spike issue at the ADC output not resolved

Please find the attachment for filtering section . We have used two ADC08200_filter_amplifier.pdf paths, one with bypassing LPF section. Bypass path contains only voltage follower (used part LMH6702), we could not able to reduce the spikes at the output of ADC. Also added 50ohm series resistor, but no improvement in output spike reduction. Kindly suggested any impudence matching required between 50ohm trace to ADC input (1Mohm), added 50ohm shunt resistor no improvement observed. 

Our requirement of output code variation should be within 5 to 6 counts, but we observing at least 100 count variations due to spikes at ADC output

Please find the attachment for ADC output code plot (Xilinx chipscope plot), which is having spikes and 1MHz_1V_200nS_Pulsewidth_input_to ADC08200.pdf ADC analog pulse input (1MHz, 200nS Pulse width, 1V input level)

  • 0
    Prodigy 110 points
    LPF part LT6600 added in front of ADC along with voltage follower using LMH6702, but spike issue at the ADC output not resolved
  • 0 in reply to Raghavendra Mendon
    Prodigy 110 points

    Please find the attachment for filtering section. We have used two paths, one with bypassing LPF section. Bypass path contains only voltage follower (used part LMH6702), we could not able to reduce the spikes at the output of ADC. Also added 50ohm series resistor, but no improvement in output spike reduction. Kindly suggested any impudence matching required between 50ohm trace to ADC input (1Mohm), added 50ohm shunt resistor no improvement observed. 7532.ADC08200_filter_amplifier.pdf

  • 0 in reply to Raghavendra Mendon
    Prodigy 110 points
    Our requirement of output code variation should be within 5 to 6 counts, but we observing at least 100 count variations due to spikes at ADC output
  • 0
    Prodigy 110 points
    Please find the attachment for ADC output code plot (Xilinx chipscope plot), which is having spikes and ADC analog pulse input (1MHz, 200nS Pulse width, 1V input level)
  • 0
    Prodigy 110 points

    7888.1MHz_1V_200nS_Pulsewidth_input_to ADC08200.pdfPlease find the attachment for ADC output code plot (Xilinx chipscope plot), which is having spikes and ADC analog pulse input (1MHz, 200nS Pulse width, 1V input level)

  • 0 in reply to Raghavendra Mendon
    TI__Mastermind 44560 points

    Hi Raghavendra

    Do you have the ability to change the timing of when the ADC data bits are captured into the FPGA? If so, try capturing the data values earlier or later to see if that helps. I think it is possible that the bits are being captured too close to when they are transitioning between the previous and next values. Since this ADC does not have a dedicated output DATA CLK it is tricky to perform data capture, and it may be necessary to adjust the data capture strobe time to find the best (most stable data) timing point.

    Can you share a text file containing the output data for several cases:

    1) DC input to ADC - input near mid-scale

    2) DC input to ADC - input just above Vrb voltage

    3) Pulse input to ADC

    Best regards,

    Jim B

  • 0 in reply to Jim Brinkhurst1
    Prodigy 110 points

    Hi Jim,

    Do you have the ability to change the timing of when the ADC data bits are captured into the FPGA? If so, try capturing the data values earlier or later to see if that helps. I think it is possible that the bits are being captured too close to when they are transitioning between the previous and next values. Since this ADC does not have a dedicated output DATA CLK it is tricky to perform data capture, and it may be necessary to adjust the data capture strobe time to find the best (most stable data) timing point.

    Ans: While capturing data we delayed by 6 clock cycle as per ADC datasheet

    Can you share a text file containing the output data for several cases:

    1) DC input to ADC - input near mid-scale

    DC_midpoint_1.2V.rar

    2) DC input to ADC - input just above Vrb voltage

    DC_VRB_400mV.rar

    3) Pulse input to ADC

    Pulse_VRB_400mV.rarPulse_VRT_1.8V.rarPulse_mid_point_1.2V.rar

  • 0 in reply to Raghavendra Mendon
    TI__Mastermind 44560 points

    Hi Raghavendra

    Can you try delaying the capture instant by fractions of a clock cycle?

    That will be necessary to set the capture strobe instant in between the transition points of the data waveform.

    Best regards,

    Jim B

  • 0 in reply to Jim Brinkhurst1
    Prodigy 110 points

    Hi Jim,

    Kindly suggest any specific delay we need add? this delay with respect what?

    We added 6 sampling clock cycle delay for capturing data as per datasheet. Is this not enough?

    Thanks and regards,

    Raghavendra

  • 0 in reply to Jim Brinkhurst1
    Prodigy 110 points
    Hi Jim,

    Kindly suggest any specific delay we need add? this delay with respect what?

    We added 6 sampling clock cycle delay for capturing data as per datasheet. Is this not enough?

    Thanks and regards,

    Raghavendra
  • 0 in reply to Raghavendra Mendon
    TI__Mastermind 44560 points

    Hi Raghavendra

    A 6 sampling clock delay will compensate for the latency of the ADC converter. It will not optimize the timing between the ADC data waveform and the sampling of that waveform by the FPGA.

    The FPGA data capture timing needs to be fine-tuned to compensate for the tOD (time from ADC rising input clock edge to when data transition is at 50% complete) and tOH (time from ADC rising input clock edge to when data transition is 10% complete) values of the ADC. (See Figure 2 of the datasheet). The values of these parameters are less than one clock period. Since there is variation in these parameters (mainly part to part variation, but some temperature variation as well) the ideal design would include some adjustment of the strobe timing to find the best capture point (minimum glitches or noise in the captured data).

    Best regards,

    Jim B