DAC38J82EVM: SYSREF not detected in FPGA

Deepak,

It appears you are not using the TSW14J10EVM and connecting the DAC EVM directly to the KC705, correct? FYI, the KC705 only has 4 serdes lanes routed so you cannot operate in 8 lane mode. If you are following slau547b, your clock settings used by the KC705 are probably wrong. Download the TSW14J10EVM User's Guide as this will provide a better example of what you are trying to accomplish.

Regards,

Jim 

Yes, I am not using TSW14J10EVM. I am directly connecting FPGA board (KC 705 based) to DAC board. based on user Guide, I tried the following config:

Device  38J82

DAC data input rate 184.32

SerDes Lanes: 2

Interpolation; 2

SERDES LineRate: 3686.4 Mbps

DAC o/p rate: 368.64 MSPS

FPGA clock: 184.32 MHz

FPGARef_clk (clkout0_1): Divider: 10

FPGA_global_clock(clkout12_13): Divider: 20

The status of JESD is as seen from FPGA

TX_SCRAMBL_REG 0x00000000

TX_SYSREF_CTRL_REG 0x00010001

TX_ILA_MULTI_REG 0x00000003

TX_TEST_MODE_REG 0x00000000

TX_ERROR_STAT_REG0 0x00000000

TX_F_REG 0x00000000

TX_K_REG 0x00000013

TX_LANES_REG 0x00000003

TX_SUBCLASS_REG 0x00000002

TX_SYNC_STAT_REG 0x00000001

TX_ERROR_STAT_REG1 0x00000000

The SYSREF sync bit is still not seen in FPGA.

How do I make sure from DAC whether JESD is in SYNC?

Thanks

Jim,

DAC gui:----------
DAC data input rate 184.32
SerDes Lanes: 2
Interpolation; 2
SERDES LineRate:1843.2 Mbps
DAC o/p rate: 184.3 MSPS
FPGA clock: 184.32 MHz
FPGARef_clk (clkout0_1): Divider: 10
FPGA_global_clock(clkout12_13): Divider: 10
LMFK = 2,2,2,10,1, Scrambling = OFF (same as default settings)

SUBCLASS: 1

FPGA settings:-----
TX_SCRAMBL_REG 0x00000000
TX_SYSREF_CTRL_REG 0x00010001
TX_ILA_MULTI_REG 0x00000003
TX_TEST_MODE_REG 0x00000000
TX_ERROR_STAT_REG0 0x00000000
TX_F_REG 0x00000001

TX_ILA_MULTI_REG 0x00000001
TX_K_REG 0x00000009
TX_LANES_REG 0x00000003
TX_SUBCLASS_REG 0x00000001
TX_SYNC_STAT_REG 0x00000001
TX_ERROR_STAT_REG1 0x00000000

In FPGA, I used K= 10-1 = 9, F=2-1=1.

Let me know if there is any discrepancy.

Thanks

Deepak,

The DAC o/p rate will be twice the input data rate since you have interpolation = 2. So this clock needs to be 368.64MHz. The Xilinx ref clk = 184.32 and the core clk = 92.16MHz. If you use the DAC EVM in external clock mode, provide a 368.64MHz clock, and use the following dividers:

DAC CLK  div by 1

REF CLK div by 2

Core clk div by 4

Regards,

Jim  

Hello Jim,

Thanks for the update. I am using Onboard clock. Is DAC clock divider auto configured, as it is set to 8? I have set dividers for REF_CLK =16, and FPGA_clk(core)= 32

DAC gui:----------
DAC data input rate 184.32
SerDes Lanes: 2
Interpolation; 2
SERDES LineRate:3686.4 Mbps
DAC o/p rate: 368.6 MSPS
FPGA clock: 92.16 MHz
LMFK = 2,2,2,10,1, Scrambling = OFF (same as default settings)

On FPGA side I still can see only SYNC signals:

TX_SYNC_STAT_REG 0x00000001

Also, I can see TX_SYNC. I still cannot see SYSREF sync(even after trigerring SYSREF using step 3 in GUI), and S_AXIS_TX_TREADY at the input of JESD204 core

The DAC GUI alarms do not show errors on the lanes detected.

Another issue I see is during GUI set up process, resetting DAC core (step 2), does not even set the TX_SYNC.

Thanks,

1423.DAC37J82_222_KC705.pptxDeepak,

I suggest you get your setup working using the example attached. Once you have established a link and receiving proper outputs from the DAC, you can start adjusting parameters to meet your needs. How are you verifying you are sending proper data out of the KC705? Are you using Chipscope?

Regards,

Jim