• State Resolved
  • Locked Locked
  • Replies 2 replies
  • Subscribers 46 subscribers
  • Views 346 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADC12J4000: Calibration Requirements and access to calibration registers

Gianpiero Panci
Prodigy 40 points
Part Number: ADC12J4000

I would need some clarification on the calibration function of the device and its requirements.

The component will be used in a receiver that will have to change sampling frequency quickly (in the order of dozens of us), I would need a confirmation that it is possible to directly write the calibration data without repeating the calibration procedure at each sampling frequency change. From the datasheet I saw that the component self-calibration procedure lasts a lot (hundreds of ms). Does the calibration procedure necessarily need to be repeated at each frequency change? Is it possible to directly write the vector of calibration parameters? (from datasheet would say yes) The calibration parameters that the calculation procedure can depend on factors or parameters ranging from reset to reset?

To be clear, the following procedure is feasible?

1. I use a specific sampling frequency FS0 and I calibrate for that, and save calibration values from ADC registers;

2. I change the sampling frequency FS1 for a period of time;

3. I return to FS0, I need to repeat the calibration process or I can simply reload the calibration values got in step 1.

Thank you in advance for the support

Gianpiero

  • 0
    TI__Mastermind 43870 points
    Hi Gianpiero
    Your procedure should work, writing the calibration values for each sample rate. The performance of the ADC should be OK as long as the die temperature is within 20 degrees of the temperature used to generate those calibration values.
    For small changes in sample rate it may not be necessary to re-calibrate the ADC. The larger the change in sample rate, the more degradation in performance will occur of the ADC is not re-calibrated, or has new calibration settings for that clock rate loaded.
    Please be aware that if you are changing the ADC clock rate, the FPGA clock rate and SYSREF will also need to change, and the JESD204B link will need to be re-started after the sample rate change.
    Best regards,
    Jim B
  • 0 in reply to Jim Brinkhurst1
    Prodigy 40 points

    Thank you for the information, we have planned the development the board in the next year.