ADC12D1600QML-SP: Large amplitude attenuation under higher frequency and Clock frequency≥800MHZ

Hi kpk
When you are using the ADC with clock rate >800 MHz please make sure to configure the device in non-LSPSM mode. Maximum clock rate for LSPSM mode is 800 MHz.
Do you have the ADC configured for DES or non-DES mode sampling?
What is the input frequency you are applying, and how much applied power is required to reach full scale levels with the ADC?
Figure 40 in the ADC12D1600QML-SP datasheet shows the typical insertion loss that can be expected in non-DES and DES sampling modes.
Best regards,
Jim B

hi Jim,

Our clock rate sampling is 320Mhz,We Configure the device in non-LSPSM Mode and non-DES Mode

Hi kpk

For a clock rate of 320 MHz I recommend LSPSM mode for best performance and lowest power consumption. Non-LSPSM should work fine, but will have slightly worse SFDR performance and higher power consumption for the same clock rate.

For non-DES mode there shouldn't be a large change in insertion loss between 100 MHz and 1200 MHz, as shown in the datasheet. If there is a big difference it may be due to other input signal path components, baluns, etc.

The mode used (LSPSM versus non-LSPSM should change the insertion loss or effective full scale input amplitude. There are other differences between these modes (output data clocking, etc.) that may be causing other problems which appear to be affecting the amplitude. One way to confirm proper data capture is to use the Test Pattern Output mode to verify the received patterns match what is shown in the datasheet.

Can you provide schematics for the input signal path up to the ADC inputs and all ADC I/O?

Please provide the logic state of all control pins and if Extended Control Mode is used please send the configuration settings loaded to all registers.

Hopefully some additional information will help us understand and resolve the issues causing the unexpected behavior.

Best regards,

Jim B