DAC38J84: Jesd204 interface latency

ADC chip will give a Channel consistency parameter,e,g,

any such parameters for DAC38J84(4 independent channel mode with real input)?

Min,

There are several factors that are involved with the JESD delay such as the elastic buffer size, lane trace length, LMFC period, ect... See if this attached document helps you.

Regards,

Jim

JESD204B Achieving Deterministic Latency_April_2016.pptxMin,

File attached now.

Regards,

Jim

Hi,

The elastic buffer delay should within a LMFC period,since the earlist and latest lan arrival difference should within a LFMC,

the RX delay and Lane delay can be read from datasheet and PCB trace ,so the max link latency can ba estimated if de_serializer delay is know,am i right? 

Hi,

Hope the picture below further clarify your query.

Regards

Ghafoor

Hi,all

Tx_delay = de_serializer delay + Elastic_buffer delay,

and Elastic_buffer delay < a LMFC period;

so to estimate max Tx_delay value,

I need de-Serializer delay parameter ,this should be a Determined value!