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CCS/ADS1282: ADS1282 with TMS320C6701

Part Number: ADS1282
Other Parts Discussed in Thread: TMS320C6701, , SMJ320C6701, TMS320VC5507, DAC121S101, ADC128S102

Tool/software: Code Composer Studio

I want to interface ADS1282 with TMS320C6701 processor.  I have connected the McBSP0 port signals to ADS1282.  DX0 to DIN of ADS1282, FSX0 to sync input of ADS1282, DRDY  output to FSR0 of DSP and DOUT to DR0 of DSP.

I want to operate the ADS1282 in continuous conversion mode with 2000 or 1000 SPS rate with handshaking by the DSP, without loosing any data.  I want to switch channel and PGA gain once in every one second. My input is a ramping signal from -1.25V to +1.25V with 10 to 100HZ rate.  I tried some code with about 100/160KHz SCLK, in command based single conversion mode. But I am not getting any DOUT when data is read, rather getting some DOUT when the ADS1282 is being configured. The sequence of register values are: 0x11, 0x41, 0x01, 0x52, 0x08, ox12 and then ox00, ox00, ox00 and ox00 for four bytes of DOUT.  But my actual requirement is continuous conversion mode with multiple sync pulse. That is, one conversion against each sync pulse.

I want to know the following.

1, What is the mode the McBSp should be configured? Is it SPI Master or Independent McBSP Transmit/ Receive?

2. Provide the value for all the McBSP registers.

3. What is the sequence for configuring the ADS1282 registers?

4. What are the values for to be written to the registers?

5. How to read data from the converter?

6. How to synchronize the data read with the DRDY out put from the ADS1282?

7. How to convert the 32bit data to corresponding analog value?

Kindly respond fast, as this is for an urgent project.

Regards,

Pradeepkumar, Project Manager

  • Hello,
    This question is best served in the Data Converters Forum. I will move it there

    Thanks
    ki
  • Hi Pradeepkumar,

    Welcome to the TI E2E forums!

    I'll try to answer you questions as best I can... I'm mostly familiar with the ADS1282 and not as familiar with the TMS320C6701 processor, so if you have additional questions regarding the processor I'll see if I can get someone on the processor side of things to jump in and help with those particular questions.

     

    The ADS1282 digital interface is SPI-compatible. It will behave as an SPI-slave device and will communicate using SPI mode 0 (CPOL = 0; CPHA = 0), when the /CS pin is low. From you description, it seems like you are using the FSX pin on the processor to control the SYNC pin on the ADS1282, instead of the /CS pin. Are you controlling the /CS pin from a separate GPIO? Generally, the FSX pin is used to control the ADC's /CS pin; however, due to the variable-length SPI commands used by the ADS1282, you may need to configure the FSX pin as a GPIO and manually set it low when you want to communicate with the ADC.

    Also keep in mind that the ADS1282 has a flat-passband FIR filter that requires about 63 conversion cycles to settle. Each time you toggle the SYNC pin (or switch input channels) you will abort the current ADC conversion and restart the conversion process. If you are toggling the SYNC pin too often you may not be allowing enough time for the conversion to complete which may be why you are not reading any data.

    Also, when using the Continuous SYNC mode, you will need to ensure that the SYNC pulse corresponds to an integer number of ADC conversion periods, accurate to within +/- 0.5 fCLKs, otherwise you will also abort and restart the current ADC conversion. I'm not sure if this is your intended use case...Do you need to ensure that multiple ADCs are synchronized, or simply command the ADC to provide 1 conversion result with each SYNC pulse? For the later use case, I would recommend using the Pulse SYNC mode (which is the default configuration of the ADS1282).

     

    PRADEEPKUMAR PADANNAYIL said:
    The sequence of register values are: 0x11, 0x41, 0x01, 0x52, 0x08, ox12 and then ox00, ox00, ox00 and ox00 for four bytes of DOUT.

    Note that the "0x41, 0x01, 0x52, 0x08" sequence of commands are configuring the CONFIG0 and CONFIG1 register to their default values.

    Before reading data, you will need to wait until the /DRDY pin goes low. Usually /DRDY is connected to a GPIO interrupt on the processor to trigger the RDATA  (read data) operation. If you read data prior to when the conversion completes you will likely see no activity on DOUT, unless a conversion has already completed in which case you may see a repeat of the previous conversion result.

     

    Regarding your specific questions:

    1. I'm not particularly familiar with the McBSP modes; however, the processor will need to provide the SCLK and control /CS to allow for variable length SPI commands.

    2. I would refer you to this reference guide for help:
       

    3. Refer to section 12 in the ADS1282 datasheet for an overview of the high-level programming sequence. For register configurations, there isn't any required sequence other than ensuring that the device is in SDATAC mode before writing to the device registers (by sending the SDATAC command or 0x11, as you showed in your example).

    4. This will depend on your application and how you want the ADS1282 to run (SYNC mode, data rate, etc.). Some registers you may be able to set once during initialization. However, for more dynamic settings, like the input MUX channel selection, you will need to reprogram these register regularly between ADC conversions. I would refer you to section 11 in the ADS1282 datasheet for more details on the register configurations. If you have any specific questions about different modes or particular registers, I'll be glad to try to answer those kinds of questions.

    5. There are two ways to read data...by command or in continuous (RDATAC) mode. In both modes you will need to wait for the /DRDY signal to go low (indicating that an ADC conversion has completed). When reading by command you will send the RDATA command followed by "0x00" bytes to clock out the data. In RDATAC mode you only need to clock out the data (by sending "0x00" bytes).

    6. This can be done by polling the /DRDY pin or using an interrupt. Generally, I recommend using interrupts so as not to unnecessarily use up processor bandwidth and to ensure a more timely response, should the processor be busy performing another process. Reading data should be handled quickly to ensure that you are not reading data during the next /DRDY low occurrence, since this can result in corrupted data which is a mix of the old and new data.

    7. Please refer to this E2E post for a thorough explanation of the ADS1282 data formatting:
       

    I hope that helps!

    Best regards,
    Chris

  • Dear Christopher,

    Thank you so much for the quick reply.

    I am giving my response to the following points in your reply.
    1. "Are you controlling the /CS pin from a separate GPIO?"
    The ADS1282 do not have /CS pin, so I am not using /CS pin
    Presently the FSX pin configured as FSX of McBSP.
    2." ADS1282 has a flat-passband FIR filter that requires about 63 conversion cycles to settle. Each time you toggle the SYNC pin"
    Does it require 63 conversion cycles to settle when using the Continuous SYNC mode, ensuring that the SYNC pulse is given as a clock which corresponds to an integer number of ADC conversion periods, accurate to within +/- 0.5 fCLKs.?
    Does it require 63 conversion cycles to settle for each conversion in the continuous conversion mode with single sync pulse?
    3. Also, when using the Continuous SYNC mode, you will need to ensure that the SYNC pulse corresponds to an integer number of ADC conversion periods, accurate to within +/- 0.5 fCLKs, otherwise you will also abort and restart the current ADC conversion"
    Does the above mentioned aborted conversion takes another 63 conversion cycles to settle?
    4. ."Do you need to ensure that multiple ADCs are synchronized, or simply command the ADC to provide 1 conversion result with each SYNC pulse?"
    I need to control and acquire data from one ADC only

    5." Before reading data, you will need to wait until the /DRDY pin goes low. Usually /DRDY is connected to a GPIO interrupt on the processor to trigger the RDATA (read data) operation. If you read data prior to when the conversion completes you will likely see no activity on DOUT, unless a conversion has already completed in which case you may see a repeat of the previous conversion result."
    I think this is my issue, presently Data read by sending 4 bytes of 0x00 is not sent by synchronizing, rather sent after a delay. I have tried 1ms, 2ms and 64ms delays also but no DOUT from the converter. I feel there is one more issue. Since I am operating McBSP in SPI mode the Frame sync FSX also is going to the Sync input of ADS1282 every time I send 0x00 to collect data. This may be triggering another new conversion and hence no data. So, I think I have to reconfigure the McBSP to disable FSX every time I send the ox00 bytes to collect the data.
    Is there any other way?
    I want to use continuous conversion mode with single sync (FSX) pulse to initiate the conversations. Is it OK?

    I am providing only Power On Reset to the Resent pin. Is it required to reset the device using some GPIO also?

    How the Modulator data output pins M0 (pin9) and M1 (pin8) be wired?


    How the Modulator clock output pins MCLK (pin7) be wired?

    Regards,
    Pradeep.
  • Hi Pradeep,

    1. You are correct, there is no /CS pin on the ADS1282; this device's SPI is always active. However, I'm still unsure about whether or not the FSX pin would be able to provide an accurate SYNC clock for the ADS1282. In order to use the continuous sync mode on the ADS1282, you would normally want the SYNC clock to be derived from the ADC's master clock to ensure that these clocks do not drift with respect to one another.
       

    2. If the SYNC clock aligns with the ADC's conversion period, nothing happens (the ADC will continuously provide data at the end of each conversion period). It is only when you first start converting or when you restart the conversion (as in the case when the SYNC clock is out of alignment with the ADC's conversion period) that you are required to wait for the filter to settle again.

      In pulse sync mode, a SYNC command will always reset the digital filter and require you to wait for the filter to settle again.

      Please note: It is only the FIR filter that requires 63 conversion periods to settle. The SINC filter will settle much faster (~5 conversion periods). Refer to table 35 in the datasheet for the exact timing.


    3. Yes. However, I believe that in continuous sync mode you will still see /DRDY pulse low each conversion period; you will get invalid data (all 0's or all 1's) until the filter has re-settled.
       

    4. If you are just using the one ADC, then I don't see a benefit to using the continuous sync mode... The intent of that mode is to ensure that multiple ADCs stay in sync, or else restart the out-of-sync ADCs to get them back in sync with the others.
       

    5. That makes sense to me... I would disable the FSX pin functionality and configure as a GPIO, that way you are not re-synchronizing the part each time you read data.

     

    Regarding your additional questions...

    PRADEEPKUMAR PADANNAYIL said:
    I want to use continuous conversion mode with single sync (FSX) pulse to initiate the conversations. Is it OK?

    This works but you might as well use pulse sync mode, since in pulse sync mode you know that every time you toggle the SYNC pin that the ADC will re-synchronize.
     

    PRADEEPKUMAR PADANNAYIL said:
    I am providing only Power On Reset to the Resent pin. Is it required to reset the device using some GPIO also?

    It is a good practice to reset the device after power up. I don't think you need to control the /RESET pin with a GPIO since you can also send the SPI command to reset the device. If you don't use the /RESET pin, then make sure you pull it high to prevent it from floating.
     

    PRADEEPKUMAR PADANNAYIL said:
    How the Modulator data output pins M0 (pin9) and M1 (pin8) be wired?
    How the Modulator clock output pins MCLK (pin7) be wired?

    If you are not using the ADS1282 in modulator mode, then tie M0, M1, and MCLK to either DVDD or GND.

     

    Best regards,
    Chris

  • Dear Chris Sir,

    In  continuation of  my previous doubts.  I want collect 32 bit data from ADS1282 ADC in SPI mode.  I have connected the DSP SMJ320C6701 McBSP0 port to the ADS1282.  The DSP_DX0 is connected to DIN of  ADS, DSP_CLKX0 is connected to SCLK of ADS,  The DOUT form the ADS is connected to the DSP_DR0,  the #DRDY from ADS is connected to the DSP_FSR0.  This CLK of the ADS1282 is provided from an independent 2MHz CMOS oscillator.  THe DSP clock is another  24MHz CMOS oscillator.

    In this way how to collect data  through SPI the from ADS1282 in continuous mode at 2000 and 4000 SPS?

    Is it possible to give a sample assembly code for doing this?

    Kindly help.

    Regards,

    Pradeep.

  • Dear Chris Sir,

    Subject: ADS1282 and DSP320C6701 SPI interfacing issue

    In  continuation of  my previous doubts.  I want collect 32 bit data from ADS1282 ADC in SPI mode.  I have connected the DSP SMJ320C6701 McBSP0 port to the ADS1282.  The DSP_DX0 is connected to DIN of  ADS, DSP_CLKX0 is connected to SCLK of ADS,  The DOUT form the ADS is connected to the DSP_DR0,  the #DRDY from ADS is connected to the DSP_FSR0.  This CLK of the ADS1282 is provided from an independent 2MHz CMOS oscillator.  THe DSP clock is another  24MHz CMOS oscillator.

    In this way how to collect data  through SPI the from ADS1282 in continuous mode at 2000 and 4000 SPS?

    Is it possible to give a sample assembly code for doing this?

    Kindly help.

    Regards,

    Pradeep.

  • Hi Pradeep,

    If you are intending to use the ADS1282's FIR filter at 2 kSPS and 4 kSPS, then you'll need to supply the ADC with a 4.096 MHz clock, otherwise with a 2.048 MHz clock you'd need to program the ADC for twice the nominal data rate.

    You're hardware connections look okay... I was comparing them to the connections made on the ADS1282EVM which connects to a McBSP port on the TMS320VC5507. The only thing I'm unsure about is whether or not "FSR" (frame sync receive) can be used for the /DRDY input. On the ADS1282EVM the /DRDY pin connects to the "FSR" pin AND an external interrupt pin, but I don't know which pin was used by the software to trigger a data read operation.

    As far as software examples go, what is on TI.com is most likely all of the available examples we have... I referenced the "TMS320C6000 DSP
    Multichannel Buffered Serial Port (McBSP) Reference Guide" above. The only other code resource I was able to find was the "TMS320C6000 Chip Support Library", found here:
    http://www.ti.com/tool/sprc090

    You might try look or asking in the C6000 Single Core DSP E2E Forum to see if anyone there is able to help with some SPI example code for that DSP. Here is the link to that forum:
    e2e.ti.com/.../

    Best regards,
    Chris

  • Dear Chris Sir,

    Thanks a lot for the help. 

    One issue of Sampling rate is answered by you.   I had observed that it was always at half rate than specified in the datasheet. OK, we have already decided to take care of this by higher rate selection. We actually need 1000SPS and below. So it is OK to have 2MHz.

    Coming to my actual issue. I want to know whether with true SPI, can I collect data at 1000SPS in continuous sampling mode.   I can connect the /DRDY to the FSR pin.  But in true SPI mode (that means, McBSP with clock stop CLKSTP bit set) FSR has no role and the McBSP disables it if I am right. 

    The document "SPRU580G–December 2006"  "Multichannel Buffered Serial Port (McBSP)" page  59  says that "The FSR and CLKR signals should not be used in SPI mode."

    That is why I could not use FSR, even though I have connected /DRDY to FSR.

    I could not find any way to use FSR in SPI mode. 

    I want to avoid using the interrupt as I am using the DAC121S101 using the same SPI port in fast sweep mode from min to Max.  It requires a continuous uninterrupted clock to avoid glitches.  If I use the interrupt, every 1ms the DAC will be interrupted and a glitch will appear in its output.

    So kindly find a way out to read the ADS1282 using the SPI interface either in true SPI mode or any other modes of the McBSP.

    Regards,

    Pradeep.

  • Hi Pradeep,

    I'm sorry for the delay. I'm trying to find someone who supports the TMS320C6701 who would be better able to answer your latest questions.

    Best regards,
    Chris
  • Dear Chris Sir,

    Thank you for all the support.

    I have decided to use the ADS1282 DRDY output as an interrupt to synchronize the ADS1282 data read/ configure, ADC128S102 data read, and DAC121S101 update.

    The problem of interfacing all three using single SPI (DSP320c6701 McBSP0 port) is solved but I am again troubled by some intermittency in operation as detailed below.

    Presently I am using the DRDY output from the ADS1282 ADC to synchronize the ADS1282 data read and DAC update, which are in continuous loop operation. Whenever the ADS output is ready the DRDY will go low. On power ON the DRDY is coming at 2ms rate instead of 1ms due to 2MHz clock instead of the 4MHz rated input. This is OK for me.

    As the program starts, it first configures the ADC128s102 and then the ADS1282 (for 1ms rate, ie 2000SPS @2MHz) and then DAC.

    What we have observed is:

    1, The ADS1282 takes multiple attempts from 2 to more than 10 attempts before it is reconfigured (programmed). All these attempts are in a loop with same McBSP parameters and ADS1282 programming byte sequence.

    2. Some times the ADS1282 fails to update even after tens of attempts and then fails to produce DRDY output stopping the entire acquisition program which depends on it to synchronize all the actions.

    If the ADS1282 is getting programmed in a few attempts, then the program works continuously without any issue and gets reprogrammed in every 3 seconds (once in every loop) for several tens of minutes.

    We are not able to understand the reason for ADS1282 not getting programmed on first attempt.

    We also do not know why the ADS1282 is not at all getting programmed even after several attempts.

    What is more dangerous is that the ADS1282 stops producing DRDY output after some time, if it could not be programmed.

    Only issue I can see is that the ADS1282 gets clock when I update the DAC, as it is shared between these.

    1. Will any zeros getting shited to ADS1282 during DAC update hamper its programing?
    2. How does the ADS1282 know that all eight bits for its programming are shifted in?
    3. When does it start counting the clock?
    4. Does the Sync pulse help synchronise the ADS1282 programming clocks and data?
    5. Or does it shift in data simply on every clock and start acting whenever it gets 8 bits?
    6. If that is the case what is the time it will wait to see that no more clock and data is coming, before it start executing the data?

    Kinldy reply fast and give us a solution.

    Regards,
    Pradeep.
  • Hi Pradeep,

    PRADEEPKUMAR PADANNAYIL said:
    Only issue I can see is that the ADS1282 gets clock when I update the DAC, as it is shared between these.

    I was just about to ask if you were sharing the same SPI signal between devices...

     

    To answer your questions:

    1. Since the ADS1282 does not have a /CS pin, any time you send an SPI command to another device on the same SPI bus this command will also get interpreted by the ADS1282. Likely, this could be the cause of your communication issues.
    2. The ADS1282 is essentially counting SCLKs. This works fine as long as the MCU and the ADC remain in sync...This can become a problem if a glitch occurs on SCLK, such that the ADC thinks it is one SCLK ahead of the MCU.

    3. The counting begins after the device releases out of internal reset (during power-on, see figure 50 or 51 depending on which datasheet for the ADS1282 you're looking at), after a time-out (SCLK held low for 65 DRDY periods), and after an SPI command completes.

    4. If I understand you question correctly, the SYNC pulse does not "reset" the clock counting on the SPI interface.

    5. Correct, after transmitting an 8-bit command the ADC looks for the next 8-bit command.

    6. In general, the ADC starts executing the command on the next rising edge of ƒCLK after the eighth rising edge of SCLK for that command, in other words right after receiving the command.

    If you can, I would recommend using a separate SPI (or McBSP) interface for the ADS1282, OR alternatively, gating the SCLK to the ADS1282 when you are not communicating with it, as shown in the attachment on this E2E post:

    Here is the plain text URL, in case the multimedia link above doesn't work: "e2e.ti.com/support/data_converters/precision_data_converters/f/73/p/291510/1016953#1016953"

    Best regards,
    Chris

  • Dear Chris Sir,

    Thank you for all the support. 

    I have decided to use the ADS1282 DRDY output as an interrupt to synchronize the ADS1282 data read/ configure, ADC128S102 data read, and DAC121S101 update. 

    The problem of interfacing all three using single SPI (DSP320c6701 McBSP0 port) is solved but I am again troubled by some intermittency in operation as detailed below. 

    Presently I am using the DRDY output from the ADS1282 ADC to synchronize the ADS1282 data read and DAC update, which are in continuous loop operation. Whenever the ADS output is ready the DRDY will go low. On power ON the DRDY is coming at 2ms rate instead of 1ms due to 2MHz clock instead of the 4MHz rated input. This is OK for me. 

    As the program starts, it first configures the ADC128s102 and then the ADS1282 (for 1ms rate, ie 2000SPS @2MHz) and then DAC. 

    What we have observed is: 

    1, The ADS1282 takes multiple attempts from 2 to more than 10 attempts before it is reconfigured (programmed). All these attempts are in a loop with same McBSP parameters and ADS1282 programming byte sequence. 

    2. Some times the ADS1282 fails to update even after tens of attempts and then fails to produce DRDY output stopping the entire acquisition program which depends on it to synchronize all the actions. 

    If the ADS1282 is getting programmed in a few attempts, then the program works continuously without any issue and gets reprogrammed in every 3 seconds (once in every loop) for several tens of minutes. 

    We are not able to understand the reason for ADS1282 not getting programmed on first attempt. 

    We also do not know why the ADS1282 is not at all getting programmed even after several attempts. 

    What is more dangerous is that the ADS1282 stops producing DRDY output after some time, if it could not be programmed. 

    Only issue I can see is that the ADS1282 gets clock when I update the DAC, as it is shared between these. 

    1. Will any zeros getting shited to ADS1282 during DAC update hamper its programing?
    2. How does the ADS1282 know that all eight bits for its programming are shifted in?
    3. When does it start counting the clock?
    4. Does the Sync pulse help synchronise the ADS1282 programming clocks and data?
    5. Or does it shift in data simply on every clock and start acting whenever it gets 8 bits?
    6. If that is the case what is the time it will wait to see that no more clock and data is coming, before it start executing the data?

    Kinldy reply fast and give us a solution. 

    Regards, 
    Pradeep.

  • Hi Pradeep,

    As Chris mentioned earlier, since the ADS1282 does not have a dedicated Chip Select pin, it will be listening/responding to anything on the MOSI feeding from the transmitter of the TMS320C6701. The DSP you are using has two McBSP peripherals, can you isolate the ADS1282 from the ADC128S102 and DAC121A101 by moving it to the other McBSP port?
  • Dear Chris Sir,

     

    I have decided to use the ADS1282 DRDY output as an interrupt to synchronize the ADS1282 data read/ ADS1282 configuration, ADC128S102 data read, and DAC121S101update. This will ensure that no SCLK is present at the time of interrupt to avoid missing of MSB of ADS1282 data.

    The problem of interfacing all three using single SPI (DSP320c6701 McBSP0 port) is solved but I am again troubled by some intermittency in operation as detailed below. 

    Presently I am using the DRDY output from the ADS1282 ADC to synchronize the ADS1282 data read and DAC update, which are in continuous loop operation, taking around 8ms per iteration. . Whenever the ADS output is ready the DRDY will go low. On power ON the DRDY is coming at 2ms rate instead of 1ms due to the usage of 2MHz clock instead of the 4MHz rated input. This is OK for me. 

    As the program starts, it first configures the ADC128s102 and then the ADS1282 (for 1ms rate, ie 2000SPS @2MHz) and then DAC.  Then it will go into a 8ms loop of 4xADS1282 Data read (4 nos of DRDY@2ms) and DAC update. This loop will continue for about 3 sec and then repeat again with the configuration of the ADC128s102 and the ADS1282(for changing channel, PGA gain and sampling rate). We are also reading the ADS1282 registers after it is configured.

    What we have observed is: 

    1, The ADS1282 takes multiple attempts from 2 to more than 10 attempts before it is reconfigured (programmed). All these attempts are in a loop with same McBSP parameters and same sequence of ADS1282 programming bytes. 

    2. Sometimes the ADS1282 fails to update even after tens of attempts and then fails to produce DRDY output, stopping the entire acquisition program which depends on it to synchronize all the actions. 

    3. If the ADS1282 is getting programmed in a few attempts, then the program works continuously without any issue and gets reprogrammed in every 3 seconds (once in every loop) for several tens of minutes. 

    4. We are not able to understand the reason for ADS1282 not getting programmed on first attempt. 

    5. We also do not know why the ADS1282 is not at all getting programmed even after several attempts. 

    6. What is more dangerous is that the ADS1282 stops producing DRDY output after some time, if it could not be programmed. 

    Only issue I can see is that the ADS1282 gets clock when I update the DAC, as it is shared between these.  Also ADS1282 may get some DIN bits without SCLK.

    7. But the main requirement is that the DRDY should be continuously coming from the ADS1282. This intermittency of DRDY output has become a major problem for us.  We are changing the channel and updating the PGA gain and sampling rate after every scan (3sec).  If the ADS1282 does not take the command, it will not change channel and thus collect data from the previous channel itself and we have no way to know which channel is being converted.  So we commanded to read the ADS1282 register to know the current channel, PGA gain and sampling rate.  So that we can use that info in the data header to avoid thinking that every alternate data is from alternate channels, as required.  But never we got any output from the ADs1282 register read operation.  So no solution yet for that.

    Another major issue is that the ADS output code do not match with the analog input given to it. This is a major and main concern for us.

    Kindly answer the following questions as early as possible>

    1. Will any bits getting shifted to ADS1282 during DAC or ADC128S102 update hamper its programing?

    2. Does a DIN input to ADS1282 without a clock, stop DRDY and stop further conversions?
    3. How does the ADS1282 know that all eight bits for its programming are shifted in?
    4. When does it start counting the clock?
    5. Does the Sync pulse help synchronise the ADS1282 programming clocks and data?
    6. Or does it shift in data simply on every clock and start acting whenever it gets 8 bits?
    7. Does any arbitrary number of SCLK input to ADS1282 with any invalid data, stop DRDY and stop further conversions?

    8. If several SCLK and DIN are fed to the ADS1282, will it take first 8 bits or last eight bits as valid input?

    9. If it take first 8 bits, then if 8 bits are not shifted in, will it wait for the remaining bits to get shifted before processing it? If so how much time it will wait? Or till what event it will wait?

    10. If it take last 8 bits, then if more than 8 bits not in multiple of 8 bits are shifted in, will it wait for the remaining bits to get shifted before processing it? If so how much time it will wait? Or till what event it will wait?

    11. On what all occasions DRDY will stop coming?

    12. Primarily, why ADS1282 is taking commands sometimes and not taking sometimes?

    13. Why the conversion output Data ready “DRDY” from the ADS1282 stops intermittently?
    14. Why ADS1282 register read operation never gives out values?
    15. Why ADS1282 converted data output do not have any relation to the input value?
    16. Is connecting the AINN1 and AINN2 inputs to GND causing this issue?


    Kindly help me get a quick answer for each and every doubts.

    Thank in advance.

    Pradeep.

  • Hi Pradeep,

    When you readback the ADS1282 registers to see if it was programmed correctly, what do you typically see on a failed attempt? Are all of the registers unchanged (still set to default values), do you find that some registers have been updated while others haven't, or do you read back junk data?

    Have you looked at the SPI communication on an oscilloscope to see if there are any signal integrity problems, or timing issues?

    To address your questions...

    1. If you accidentally shift in bits to the ADS1282 when you are not intending to, it will mess up the communication as data will be out of alignment. You might try holding SCLK low for 64 /DRDY cycles to allow the ADS1282's SPI interface to reset before you start programming the registers OR you can toggle the /RESET pin and this will also reset the SPI interface. This will help to ensure that the SPI commands and data are aligned so that the ADS1282 interprets them correctly.

    2. If you were to accidentally send a STANDBY command it might halt the /DRDY output. Also, any of the calibration commands might temporarily stop /DRDY, since calibration can take awhile.
    3. I suspect this is an internal counter; hence, why it is important to make sure SCLK is clean and glitch-free. Holding SCLK low for 64 /DRDY periods or toggling /RESET will reset this counter.

    4. With no /CS pin, the ADS1282 is always counting the clock.

    5. No. SYNC is independent of the SPI interface.

    6. Correct

    7. Yes, random or arbitrary SPI commands may in some cases be interpreted as real commands to the ADS1282 and they may cause the /DRDY output to stop.

    8. Starting with the first SCLK, each group of 8 bits will be a new command to the device.

    9. I believe the device decodes the commands after the 8th SCLK (otherwise how would it distinguish between RDATAC 0x10, and SDATAC, 0x11). If you don't complete the command, and SCLK is held low, then it waits until the timeout occurs (64 /DRDY periods). If SCLK is held high, then it will likely wait indefinitely.

    10. Completed commands will take place and then the incomplete command will wait the same way as described in question #9.

    11. There are probably a lot of ways to stop /DRDY from pulsing including, loss of power, loss of fCLK, holding the /RESET or /PWDN GPIO pins low, or sending the STANDBY command.

    12. It sounds like you have some kind of communication error. Likely data is getting out of alignment, such that commands to the device are being misinterpreted. I would recommend resetting the SPI interface and then trying to re-communicate with the device resolves the issue.

    13/14/15/16. I think all of these issues could be explained by misalignment of the SPI data with SCLK.

    I would highly recommend trying to gate off the SCLK signal to the ADS1282 when you are actively communicating with it. The next best solution might be to toggle the /RESET pin before using the ADS1282 to ensure a clean register configuration and start of new SPI data.

    Best regards,
    Chris

  • Dear Cris,

    Thank you so much for answering all questions.

    I have a few more questions now.

    1.  I have decided not to use SYNC input of the ADS1282 ADC, as the Frame sync output (FSX0) of DSP wired to SYNC input cannot be stopped in SPI mode communication.  So I have tested the ADS1282with SYNC input left open. 

    Can I keep the SYNC input open if I am not using SYNC input.?

    2. Can I perform Offset calibration alone, even if the input to ADS1282 is varying?

    Thanks in advance.

    Regards,

    Pradeep.

  • Hi Pradeep,

    Not a problem!

    1. I would recommend tying the SYNC pin high to ensure that the the ADC is converting and that you can issue the "SYNC" SPI command and calibration commands (which require the SYNC pin to be high). If SYNC is left floating it could cause issues with the device synchronizing when you don't want it to.

    2. You wouldn't be able to use the "OFSCAL" SPI command since it assumes that the input is a 0V-dc signal. However, if your input signal was a clean sine wave centered around 0V, I suppose you could write your own calibration routine that measured the average value of the input signal and manually programmed the OFC[2:0] registers to make the average value equal to 0. My main concern though is that this would be a more complicated offset calibration routine that requires a very clean input signal, and as a result would be more error prone than simply applying a 0V dc signal and running the "OFSCAL" command.

    Let me know if I can help with anything else.

    Best regards,
    Chris