ADS4249EVM: TCXO and filter recommended by TI are obsolete.

Aronii,

These are common wireless standard frequencies that are used by many of our customers. This is the main reason we selected these. 1G and 250MHz should not be a problem to use.

Regards,

Jim

Aronii,

Here are some data sheets I could find. We have not worked on this board for many years so some of this material may be out of date. We did use a RBP-263+ filter from Mini-circuits on our ADS42JB69EVM.

Regards,

Jim

TCO-2111series.pdfTF2-D0AD6_E06X.pdfLFCN-2750D+[1].pdf

On CDCE72010 EVM I found this:

which is the missing component on the ADS4249EVM.
It seems like this component is custom made for TI. I wonder why TI did not install it in the ADS4249 EVM?

Is there any technical reason for that or it is just another way to promote the sales of Ti's clock boards like TSW4806 ?

I wonder why no one put a note on the web page that this board does not work as is because of the missing components?

After looking at the ADS4249EVM schematics, I must say that I'm totally confused...
The CDCE72010 get the 983.04 MHz. clock at VCXO IN and VCXO INB inputs. It outputs from pin #7 a signal labeled "YOP".
This signal goes to the 491.52 MHz. filter and then to another signal names "Y0"
It makes sense that this signal is 491.52 MHz. and not near 250 MHz because it passed thru that narrow BPF.
The "Y0" signal is connected to jumper SJP6 which goes to the transformer T6.
The outputs of this transformer are CLKP and CLKM signals which goes to pins # 25 and 26 on the ADS4249 chip.
This chip is supposed to work at maximum 250 Mhz. (same as the data rate - it works using DDR interface - data from one ADC on the rising edge and data from the other ADC on the falling edge) so it should be around 250 Mhz. and not around 500 MHz.
So I wonder why did they put a 491.52 MHz. filter there?
Is it some kind of mistake or this board contains another component?

On the BOM (Excel file) it says that the component is "ADS42B29IRGC or ADS42B49IRGC". I searched TI web page for "ADS42B49" and I got this message:
"No matches found for "ADS42B29""
I searched for ADS42B49 and I found that it is the buffered version of ADS4249 - the other parameters are the same - maximum clock is also 250 MHz.

On the video they connect the TSW4806 running at 245.76 MHz.

How this component works on 491.52 MHz? And if it works on about 245 MHz. - how would this frequency pass the band-pass filter?
On the evaluation board instructions I did not find any screen which shows that the frequency to the evaluation board can be divided (like in the CDCE72010 evaluation board). However, I see that there are SPI lines coming from the USB chip. So how do I control this clock divider?

Please check the entire signal path and give me clear instruction for operating this board at 250 MHz. sampling rate.
I have already spent few hours to investigate this board. I wonder why do I have to do reverse engineering and spend more hours on finding hard to get or custom made components from other vendors in order to make this board work properly with low noise and low jitter.

Hello Dan,

I saw those 2 resistors before. I hope that we both understand that those 2 resistors are there because the filter is not there.

Otherwise - there was no need to put the filter and its surrounding components on that PCB.

If you will read this TI paper you will understand why did they put a filter there: 
http://www.ti.com/lit/an/slyt379/slyt379.pdf

They write it in the paper: "A 6-MHz, wide-bandpass filter was added to the clock input to limit the amount of wideband noise contributed to the jitter"

Actually, it is not their "invention". it is well known that a tight BPF after the first stage that divides the oscillator by 2 or 4 (to make duty cycle of exactly 50%) is the best thing to reduce phase jitter.

If you will google "phase noise band pass filters", you would see many papers discussing that and showing how the phase noise, jitter and even the SNR become better after adding such a narrow BPF there.

On ADS62P49EVM forun (see link above) even Stefan, a TI employee says:"Option 3 without a filter will result in lower SNR results due to increased jitter. If there is no bandlimit of the phase noise on the clock input, the phase noise of the other Nyquist zones will fold into the Nyquist zone and increase the noise floor degrading the SNR." 

and he is right...

My application requires a very low noise. Using the 0 Ohms resistors which bypass the filter is not an option.

So let's discuss the circuit diagram assuming that I remove the 0 Ohms resistors and put a BPF filter.

The 1 GHz. signal goes to the divider and then comes out of pin #7 of the CDCE72010. Then, it goes to the filter and to the ADC.

Does it makes sense to you that they used a 491.52 MHz filter or it is a mistake and there should be another filter around 245.7 MHz?

To my opinion it is a mistake in the drawing and a 245.7 MHz filter was supposed to be there. What do you think?

My second question which was not answered is how do I program the CDCE72010 chip on that board?

The ADS4249EVM manual does not say a word about programming the clock frequency. The only thing they say about the CDCE72010 in this manual is:

" With a 10-MHz primary reference at J19 and a 983.04-MHz VCXO on-board, the CDC
outputs a LVCMOS clock at U0P (pin 7) at 245.76 MHz. With a 491.52-MHz VCXO, the CDC outputs a
LVCMOS clock at U0P at 122.88 MHz. The clock goes through an on-board crystal BPF (Y0) and is used
as the input clock to the ADC through SJP6"

There are also parameters for setting the clock strength, setting LVDS or CMOS clock - but no way to set the division ratio - you are always stuck with the default of division by 4.

I wonder why did TI put such an expensive clock chip with no way to set the division ratio. If you know any software which can control this chip thru the on-board FTDI chip, please let me know.

If there is no way to set a different divider ratio thru TI's software, I wonder if it would be possible to publish the source code of the board control software or at least send me some documentation of the protocol for the FTDI chip. This chip is a simple UART protocol on USB - no special firmware. If you can publish the library which controls this chip - I can proceed from there.

I found an interesting drawing on the net: ADS62P49EVM. quite a similar chip but the filter is different, as I thought:

As you may see, the oscillator of that board is also 983.04 MHz. but the filter is 245.76 MHz.
Did I miss something or it is a TI mistake in the ADS4249 EVM drawing?

What about changing the sampling rate / division ratio? Any solution?

Jim,

Thanks for your input. Therefore, you must fix the drawing of the ADS4249EVM - a double frequency filter appears there.

As for my 2'nd question:

I want to change the division ratio to 5 or 6 or 8. How can I do that?

On the ADS4249EVM software there is no place to change the divider (although the clock divider is capable of such divisions).